[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL v2 12/27] target/riscv: Relax vector register check in RISCV gdbst
|
From: |
Alistair Francis |
|
Subject: |
[PULL v2 12/27] target/riscv: Relax vector register check in RISCV gdbstub |
|
Date: |
Mon, 3 Jun 2024 21:16:28 +1000 |
From: Jason Chien <jason.chien@sifive.com>
In current implementation, the gdbstub allows reading vector registers
only if V extension is supported. However, all vector extensions and
vector crypto extensions have the vector registers and they all depend
on Zve32x. The gdbstub should check for Zve32x instead.
Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
Message-ID: <20240328022343.6871-4-jason.chien@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/gdbstub.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index be7a02cd90..d0cc5762c2 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -338,7 +338,7 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
gdb_find_static_feature("riscv-32bit-fpu.xml"),
0);
}
- if (env->misa_ext & RVV) {
+ if (cpu->cfg.ext_zve32x) {
gdb_register_coprocessor(cs, riscv_gdb_get_vector,
riscv_gdb_set_vector,
ricsv_gen_dynamic_vector_feature(cs,
cs->gdb_num_regs),
--
2.45.1
- [PULL v2 02/27] target/riscv/kvm: Fix exposure of Zkr, (continued)
- [PULL v2 02/27] target/riscv/kvm: Fix exposure of Zkr, Alistair Francis, 2024/06/03
- [PULL v2 01/27] hw/intc/riscv_aplic: APLICs should add child earlier than realize, Alistair Francis, 2024/06/03
- [PULL v2 04/27] target/riscv/kvm: implement SBI debug console (DBCN) calls, Alistair Francis, 2024/06/03
- [PULL v2 06/27] target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63, Alistair Francis, 2024/06/03
- [PULL v2 05/27] hw/riscv/boot.c: Support 64-bit address for initrd, Alistair Francis, 2024/06/03
- [PULL v2 03/27] target/riscv: Raise exceptions on wrs.nto, Alistair Francis, 2024/06/03
- [PULL v2 07/27] target/riscv/kvm: tolerate KVM disable ext errors, Alistair Francis, 2024/06/03
- [PULL v2 08/27] target/riscv/debug: set tval=pc in breakpoint exceptions, Alistair Francis, 2024/06/03
- [PULL v2 11/27] target/riscv: Add support for Zve64x extension, Alistair Francis, 2024/06/03
- [PULL v2 10/27] target/riscv: Add support for Zve32x extension, Alistair Francis, 2024/06/03
- [PULL v2 12/27] target/riscv: Relax vector register check in RISCV gdbstub,
Alistair Francis <=
- [PULL v2 14/27] target/riscv/cpu.c: fix Zvkb extension config, Alistair Francis, 2024/06/03
- [PULL v2 15/27] target/riscv: Implement dynamic establishment of custom decoder, Alistair Francis, 2024/06/03
- [PULL v2 13/27] target/riscv: Fix the element agnostic function problem, Alistair Francis, 2024/06/03
- [PULL v2 17/27] target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions, Alistair Francis, 2024/06/03
- [PULL v2 09/27] trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint, Alistair Francis, 2024/06/03
- [PULL v2 18/27] target/riscv: rvv: Check single width operator for vector fp widen instructions, Alistair Francis, 2024/06/03
- [PULL v2 16/27] riscv: thead: Add th.sxstatus CSR emulation, Alistair Francis, 2024/06/03
- [PULL v2 19/27] target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w, Alistair Francis, 2024/06/03
- [PULL v2 20/27] target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions, Alistair Francis, 2024/06/03
- [PULL v2 22/27] target/riscv: do not set mtval2 for non guest-page faults, Alistair Francis, 2024/06/03