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[PULL v2 23/27] target/riscv: Remove experimental prefix from "B" extens
From: |
Alistair Francis |
Subject: |
[PULL v2 23/27] target/riscv: Remove experimental prefix from "B" extension |
Date: |
Mon, 3 Jun 2024 21:16:39 +1000 |
From: Rob Bradford <rbradford@rivosinc.com>
This extension has now been ratified:
https://jira.riscv.org/browse/RVS-2006 so the "x-" prefix can be
removed.
Since this is now a ratified extension add it to the list of extensions
included in the "max" CPU variant.
Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20240514110217.22516-1-rbradford@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 2 +-
target/riscv/tcg/tcg-cpu.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 2946ac298a..cee6fc4a9a 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1400,7 +1400,7 @@ static const MISAExtInfo misa_ext_info_arr[] = {
MISA_EXT_INFO(RVJ, "x-j", "Dynamic translated languages"),
MISA_EXT_INFO(RVV, "v", "Vector operations"),
MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"),
- MISA_EXT_INFO(RVB, "x-b", "Bit manipulation (Zba_Zbb_Zbs)")
+ MISA_EXT_INFO(RVB, "b", "Bit manipulation (Zba_Zbb_Zbs)")
};
static void riscv_cpu_validate_misa_mxl(RISCVCPUClass *mcc)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index f59b5d7f2d..683f604d9f 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -1301,7 +1301,7 @@ static void riscv_init_max_cpu_extensions(Object *obj)
const RISCVCPUMultiExtConfig *prop;
/* Enable RVG, RVJ and RVV that are disabled by default */
- riscv_cpu_set_misa_ext(env, env->misa_ext | RVG | RVJ | RVV);
+ riscv_cpu_set_misa_ext(env, env->misa_ext | RVB | RVG | RVJ | RVV);
for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
isa_ext_update_enabled(cpu, prop->offset, true);
--
2.45.1
- [PULL v2 14/27] target/riscv/cpu.c: fix Zvkb extension config, (continued)
- [PULL v2 14/27] target/riscv/cpu.c: fix Zvkb extension config, Alistair Francis, 2024/06/03
- [PULL v2 15/27] target/riscv: Implement dynamic establishment of custom decoder, Alistair Francis, 2024/06/03
- [PULL v2 13/27] target/riscv: Fix the element agnostic function problem, Alistair Francis, 2024/06/03
- [PULL v2 17/27] target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions, Alistair Francis, 2024/06/03
- [PULL v2 09/27] trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint, Alistair Francis, 2024/06/03
- [PULL v2 18/27] target/riscv: rvv: Check single width operator for vector fp widen instructions, Alistair Francis, 2024/06/03
- [PULL v2 16/27] riscv: thead: Add th.sxstatus CSR emulation, Alistair Francis, 2024/06/03
- [PULL v2 19/27] target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w, Alistair Francis, 2024/06/03
- [PULL v2 20/27] target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions, Alistair Francis, 2024/06/03
- [PULL v2 22/27] target/riscv: do not set mtval2 for non guest-page faults, Alistair Francis, 2024/06/03
- [PULL v2 23/27] target/riscv: Remove experimental prefix from "B" extension,
Alistair Francis <=
- [PULL v2 21/27] target/riscv: prioritize pmp errors in raise_mmu_exception(), Alistair Francis, 2024/06/03
- [PULL v2 24/27] target/riscv: rvzicbo: Fixup CBO extension register calculation, Alistair Francis, 2024/06/03
- [PULL v2 26/27] riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature(), Alistair Francis, 2024/06/03
- [PULL v2 27/27] disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs, Alistair Francis, 2024/06/03
- [PULL v2 25/27] target/riscv/kvm.c: Fix the hart bit setting of AIA, Alistair Francis, 2024/06/03
- Re: [PULL v2 00/27] riscv-to-apply queue, Philippe Mathieu-Daudé, 2024/06/03
- Re: [PULL v2 00/27] riscv-to-apply queue, Richard Henderson, 2024/06/04