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[PULL v2 26/27] riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vec
From: |
Alistair Francis |
Subject: |
[PULL v2 26/27] riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature() |
Date: |
Mon, 3 Jun 2024 21:16:42 +1000 |
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Commit 33a24910ae changed 'reg_width' to use 'vlenb', i.e. vector length
in bytes, when in this context we want 'reg_width' as the length in
bits.
Fix 'reg_width' back to the value in bits like 7cb59921c05a
("target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen'") set
beforehand.
While we're at it, rename 'reg_width' to 'bitsize' to provide a bit more
clarity about what the variable represents. 'bitsize' is also used in
riscv_gen_dynamic_csr_feature() with the same purpose, i.e. as an input to
gdb_feature_builder_append_reg().
Cc: Akihiko Odaki <akihiko.odaki@daynix.com>
Cc: Alex Bennée <alex.bennee@linaro.org>
Reported-by: Robin Dapp <rdapp.gcc@gmail.com>
Fixes: 33a24910ae ("target/riscv: Use GDBFeature for dynamic XML")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Acked-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240517203054.880861-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/gdbstub.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index d0cc5762c2..c07df972f1 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -288,7 +288,7 @@ static GDBFeature *riscv_gen_dynamic_csr_feature(CPUState
*cs, int base_reg)
static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
{
RISCVCPU *cpu = RISCV_CPU(cs);
- int reg_width = cpu->cfg.vlenb;
+ int bitsize = cpu->cfg.vlenb << 3;
GDBFeatureBuilder builder;
int i;
@@ -298,7 +298,7 @@ static GDBFeature
*ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
/* First define types and totals in a whole VL */
for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
- int count = reg_width / vec_lanes[i].size;
+ int count = bitsize / vec_lanes[i].size;
gdb_feature_builder_append_tag(
&builder, "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
vec_lanes[i].id, vec_lanes[i].gdb_type, count);
@@ -316,7 +316,7 @@ static GDBFeature
*ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
/* Define vector registers */
for (i = 0; i < 32; i++) {
gdb_feature_builder_append_reg(&builder, g_strdup_printf("v%d", i),
- reg_width, i, "riscv_vector", "vector");
+ bitsize, i, "riscv_vector", "vector");
}
gdb_feature_builder_end(&builder);
--
2.45.1
- [PULL v2 17/27] target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions, (continued)
- [PULL v2 17/27] target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions, Alistair Francis, 2024/06/03
- [PULL v2 09/27] trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint, Alistair Francis, 2024/06/03
- [PULL v2 18/27] target/riscv: rvv: Check single width operator for vector fp widen instructions, Alistair Francis, 2024/06/03
- [PULL v2 16/27] riscv: thead: Add th.sxstatus CSR emulation, Alistair Francis, 2024/06/03
- [PULL v2 19/27] target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w, Alistair Francis, 2024/06/03
- [PULL v2 20/27] target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions, Alistair Francis, 2024/06/03
- [PULL v2 22/27] target/riscv: do not set mtval2 for non guest-page faults, Alistair Francis, 2024/06/03
- [PULL v2 23/27] target/riscv: Remove experimental prefix from "B" extension, Alistair Francis, 2024/06/03
- [PULL v2 21/27] target/riscv: prioritize pmp errors in raise_mmu_exception(), Alistair Francis, 2024/06/03
- [PULL v2 24/27] target/riscv: rvzicbo: Fixup CBO extension register calculation, Alistair Francis, 2024/06/03
- [PULL v2 26/27] riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature(),
Alistair Francis <=
- [PULL v2 27/27] disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs, Alistair Francis, 2024/06/03
- [PULL v2 25/27] target/riscv/kvm.c: Fix the hart bit setting of AIA, Alistair Francis, 2024/06/03
- Re: [PULL v2 00/27] riscv-to-apply queue, Philippe Mathieu-Daudé, 2024/06/03
- Re: [PULL v2 00/27] riscv-to-apply queue, Richard Henderson, 2024/06/04