[PATCH 1/1] target/arm: calculate cache sizes properly

[Marcin Juszkiewicz]

Neoverse-V1 TRM says that NumSets are [27:13] not :32 like in code.

With this fix all cores which use make_ccsidr64() function have proper
size of cpu caches.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
---
 target/arm/tcg/cpu64.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index fe232eb306..98144e1d20 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -50,7 +50,7 @@ static uint64_t make_ccsidr64(unsigned assoc, unsigned 
linesize,
     sets = cachesize / (assoc * linesize);
     assert(cachesize % (assoc * linesize) == 0);
 
-    return ((uint64_t)(sets - 1) << 32)
+    return ((uint64_t)(sets - 1) << 13)
          | ((assoc - 1) << 3)
          | (lg_linesize - 4);
 }
-- 
2.45.2