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Re: [PATCH 1/1] target/arm: calculate cache sizes properly
From: |
Peter Maydell |
Subject: |
Re: [PATCH 1/1] target/arm: calculate cache sizes properly |
Date: |
Thu, 11 Jul 2024 11:19:44 +0100 |
On Wed, 10 Jul 2024 at 18:35, Marcin Juszkiewicz
<marcin.juszkiewicz@linaro.org> wrote:
>
> Neoverse-V1 TRM says that NumSets are [27:13] not :32 like in code.
NumSets in fields [27:13] is the 32-bit CCSIDR_EL1 format
(i.e. what you have when FEAT_CCIDX is not implemented).
The make_ccsidr64() function provides the 64-bit CCSIDR_EL1
format (i.e. the one when FEAT_CCIDX is implemented).
I would suspect this is an accidental error in the Neoverse-V1
TRM -- if you have access to the real hardware and can dump
the CCSIDR_EL1 value I would expect you'll see it matches
what QEMU is implementing here (and that ID_AA64MMFR2_EL1.CCIDX
also says that FEAT_CCIDX is implemented). See also the comment
"The Neoverse-V1 r1p2 TRM lists 32-bit format CCSIDR_EL1 values"
in aarch64_neoverse_v1_initfn() where we document that we
don't trust what the TRM is saying here.
How did you run into this? Is there some guest software
which is assuming the old 32-bit format and not checking
ID_AA64MMFR2_EL1.CCIDX to see if it needs to use the new one?
thanks
-- PMM