[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 10/24] hw/char/pl011: Avoid division-by-zero in pl011_get_baudrate
From: |
Peter Maydell |
Subject: |
[PULL 10/24] hw/char/pl011: Avoid division-by-zero in pl011_get_baudrate() |
Date: |
Thu, 11 Jul 2024 14:18:08 +0100 |
From: Zheyu Ma <zheyuma97@gmail.com>
In pl011_get_baudrate(), when we calculate the baudrate we can
accidentally divide by zero. This happens because although (as the
specification requires) we treat UARTIBRD = 0 as invalid, we aren't
correctly limiting UARTIBRD and UARTFBRD values to the 16-bit and 6-bit
ranges the hardware allows, and so some non-zero values of UARTIBRD can
result in a zero divisor.
Enforce the correct register field widths on guest writes and on inbound
migration to avoid the division by zero.
ASAN log:
==2973125==ERROR: AddressSanitizer: FPE on unknown address 0x55f72629b348
(pc 0x55f72629b348 bp 0x7fffa24d0e00 sp 0x7fffa24d0d60 T0)
#0 0x55f72629b348 in pl011_get_baudrate hw/char/pl011.c:255:17
#1 0x55f726298d94 in pl011_trace_baudrate_change hw/char/pl011.c:260:33
#2 0x55f726296fc8 in pl011_write hw/char/pl011.c:378:9
Reproducer:
cat << EOF | qemu-system-aarch64 -display \
none -machine accel=qtest, -m 512M -machine realview-pb-a8 -qtest stdio
writeq 0x1000b024 0xf8000000
EOF
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Zheyu Ma <zheyuma97@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240702155752.3022007-1-zheyuma97@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/char/pl011.c | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/hw/char/pl011.c b/hw/char/pl011.c
index 8753b84a842..f8078aa216d 100644
--- a/hw/char/pl011.c
+++ b/hw/char/pl011.c
@@ -87,6 +87,12 @@ DeviceState *pl011_create(hwaddr addr, qemu_irq irq, Chardev
*chr)
#define CR_DTR (1 << 10)
#define CR_LBE (1 << 7)
+/* Integer Baud Rate Divider, UARTIBRD */
+#define IBRD_MASK 0x3f
+
+/* Fractional Baud Rate Divider, UARTFBRD */
+#define FBRD_MASK 0xffff
+
static const unsigned char pl011_id_arm[8] =
{ 0x11, 0x10, 0x14, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
static const unsigned char pl011_id_luminary[8] =
@@ -374,11 +380,11 @@ static void pl011_write(void *opaque, hwaddr offset,
s->ilpr = value;
break;
case 9: /* UARTIBRD */
- s->ibrd = value;
+ s->ibrd = value & IBRD_MASK;
pl011_trace_baudrate_change(s);
break;
case 10: /* UARTFBRD */
- s->fbrd = value;
+ s->fbrd = value & FBRD_MASK;
pl011_trace_baudrate_change(s);
break;
case 11: /* UARTLCR_H */
@@ -531,6 +537,9 @@ static int pl011_post_load(void *opaque, int version_id)
s->read_pos = 0;
}
+ s->ibrd &= IBRD_MASK;
+ s->fbrd &= FBRD_MASK;
+
return 0;
}
--
2.34.1
- [PULL 00/24] target-arm queue, Peter Maydell, 2024/07/11
- [PULL 02/24] target/arm: Make vfp_get_fpscr() call vfp_get_{fpcr, fpsr}, Peter Maydell, 2024/07/11
- [PULL 03/24] target/arm: Make vfp_set_fpscr() call vfp_set_{fpcr, fpsr}, Peter Maydell, 2024/07/11
- [PULL 10/24] hw/char/pl011: Avoid division-by-zero in pl011_get_baudrate(),
Peter Maydell <=
- [PULL 19/24] target/arm: Convert SMULL, UMULL, SMLAL, UMLAL, SMLSL, UMLSL to decodetree, Peter Maydell, 2024/07/11
- [PULL 17/24] hw/misc: In STM32L4x5 EXTI, handle direct interrupts, Peter Maydell, 2024/07/11
- [PULL 04/24] target/arm: Support migration when FPSR/FPCR won't fit in the FPSCR, Peter Maydell, 2024/07/11
- [PULL 05/24] target/arm: Implement store_cpu_field_low32() macro, Peter Maydell, 2024/07/11
- [PULL 24/24] target/arm: Convert PMULL to decodetree, Peter Maydell, 2024/07/11
- [PULL 01/24] target/arm: Correct comments about M-profile FPSCR, Peter Maydell, 2024/07/11
- [PULL 13/24] target/arm: Set arm_v7m_tcg_ops cpu_exec_halt to arm_cpu_exec_halt(), Peter Maydell, 2024/07/11
- [PULL 06/24] target/arm: Store FPSR and FPCR in separate CPU state fields, Peter Maydell, 2024/07/11
- [PULL 07/24] target/arm: Rename FPCR_ QC, NZCV macros to FPSR_, Peter Maydell, 2024/07/11
- [PULL 16/24] hw/misc: In STM32L4x5 EXTI, consolidate 2 constants, Peter Maydell, 2024/07/11
- Prev by Date:
[PULL 03/24] target/arm: Make vfp_set_fpscr() call vfp_set_{fpcr, fpsr}
- Next by Date:
[PULL 19/24] target/arm: Convert SMULL, UMULL, SMLAL, UMLAL, SMLSL, UMLSL to decodetree
- Previous by thread:
[PULL 03/24] target/arm: Make vfp_set_fpscr() call vfp_set_{fpcr, fpsr}
- Next by thread:
[PULL 19/24] target/arm: Convert SMULL, UMULL, SMLAL, UMLAL, SMLSL, UMLSL to decodetree
- Index(es):