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[PULL 17/24] hw/misc: In STM32L4x5 EXTI, handle direct interrupts
From: |
Peter Maydell |
Subject: |
[PULL 17/24] hw/misc: In STM32L4x5 EXTI, handle direct interrupts |
Date: |
Thu, 11 Jul 2024 14:18:15 +0100 |
From: Inès Varhol <ines.varhol@telecom-paris.fr>
The previous implementation for EXTI interrupts only handled
"configurable" interrupts, like those originating from STM32L4x5 SYSCFG
(the only device currently connected to the EXTI up until now).
In order to connect STM32L4x5 USART to the EXTI, this commit adds
handling for direct interrupts (interrupts without configurable edge).
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Message-id: 20240707085927.122867-3-ines.varhol@telecom-paris.fr
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/misc/stm32l4x5_exti.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/hw/misc/stm32l4x5_exti.c b/hw/misc/stm32l4x5_exti.c
index b9a69a69f60..e281841dcf4 100644
--- a/hw/misc/stm32l4x5_exti.c
+++ b/hw/misc/stm32l4x5_exti.c
@@ -113,6 +113,13 @@ static void stm32l4x5_exti_set_irq(void *opaque, int irq,
int level)
return;
}
+ /* In case of a direct line interrupt */
+ if (extract32(exti_romask[bank], irq, 1)) {
+ qemu_set_irq(s->irq[oirq], level);
+ return;
+ }
+
+ /* In case of a configurable interrupt */
if ((level && extract32(s->rtsr[bank], irq, 1)) ||
(!level && extract32(s->ftsr[bank], irq, 1))) {
--
2.34.1
- [PULL 00/24] target-arm queue, Peter Maydell, 2024/07/11
- [PULL 02/24] target/arm: Make vfp_get_fpscr() call vfp_get_{fpcr, fpsr}, Peter Maydell, 2024/07/11
- [PULL 03/24] target/arm: Make vfp_set_fpscr() call vfp_set_{fpcr, fpsr}, Peter Maydell, 2024/07/11
- [PULL 10/24] hw/char/pl011: Avoid division-by-zero in pl011_get_baudrate(), Peter Maydell, 2024/07/11
- [PULL 19/24] target/arm: Convert SMULL, UMULL, SMLAL, UMLAL, SMLSL, UMLSL to decodetree, Peter Maydell, 2024/07/11
- [PULL 17/24] hw/misc: In STM32L4x5 EXTI, handle direct interrupts,
Peter Maydell <=
- [PULL 04/24] target/arm: Support migration when FPSR/FPCR won't fit in the FPSCR, Peter Maydell, 2024/07/11
- [PULL 05/24] target/arm: Implement store_cpu_field_low32() macro, Peter Maydell, 2024/07/11
- [PULL 24/24] target/arm: Convert PMULL to decodetree, Peter Maydell, 2024/07/11
- [PULL 01/24] target/arm: Correct comments about M-profile FPSCR, Peter Maydell, 2024/07/11
- [PULL 13/24] target/arm: Set arm_v7m_tcg_ops cpu_exec_halt to arm_cpu_exec_halt(), Peter Maydell, 2024/07/11
- [PULL 06/24] target/arm: Store FPSR and FPCR in separate CPU state fields, Peter Maydell, 2024/07/11
- [PULL 07/24] target/arm: Rename FPCR_ QC, NZCV macros to FPSR_, Peter Maydell, 2024/07/11
- [PULL 16/24] hw/misc: In STM32L4x5 EXTI, consolidate 2 constants, Peter Maydell, 2024/07/11
- [PULL 09/24] target/arm: Allow FPCR bits that aren't in FPSCR, Peter Maydell, 2024/07/11
- [PULL 15/24] accel/tcg: Make TCGCPUOps::cpu_exec_halt mandatory, Peter Maydell, 2024/07/11
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