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[PATCH 12/18] ppc/pnv: Add allow for big-core differences in DT generati
From: |
Nicholas Piggin |
Subject: |
[PATCH 12/18] ppc/pnv: Add allow for big-core differences in DT generation |
Date: |
Fri, 12 Jul 2024 00:18:44 +1000 |
device-tree building needs to account for big-core mode, because it is
driven by qemu cores (small cores). Every second core should be skipped,
and every core should describe threads for both small-cores that make
up the big core.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
hw/ppc/pnv.c | 43 +++++++++++++++++++++++++++++++++++--------
1 file changed, 35 insertions(+), 8 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index d2ddc49142..d7488be74c 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -141,9 +141,9 @@ static int pnv_dt_core(PnvChip *chip, PnvCore *pc, void
*fdt)
CPUPPCState *env = &cpu->env;
PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
PnvChipClass *pnv_cc = PNV_CHIP_GET_CLASS(chip);
- g_autofree uint32_t *servers_prop = g_new(uint32_t, smt_threads);
+ uint32_t *servers_prop;
int i;
- uint32_t pir;
+ uint32_t pir, tir;
uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
0xffffffff, 0xffffffff};
uint32_t tbfreq = PNV_TIMEBASE_FREQ;
@@ -154,7 +154,10 @@ static int pnv_dt_core(PnvChip *chip, PnvCore *pc, void
*fdt)
char *nodename;
int cpus_offset = get_cpus_node(fdt);
- pnv_cc->get_pir_tir(chip, pc->hwid, 0, &pir, NULL);
+ pnv_cc->get_pir_tir(chip, pc->hwid, 0, &pir, &tir);
+
+ /* Only one DT node per (big) core */
+ g_assert(tir == 0);
nodename = g_strdup_printf("%s@%x", dc->fw_name, pir);
offset = fdt_add_subnode(fdt, cpus_offset, nodename);
@@ -235,12 +238,28 @@ static int pnv_dt_core(PnvChip *chip, PnvCore *pc, void
*fdt)
}
/* Build interrupt servers properties */
- for (i = 0; i < smt_threads; i++) {
- pnv_cc->get_pir_tir(chip, pc->hwid, i, &pir, NULL);
- servers_prop[i] = cpu_to_be32(pir);
+ if (pc->big_core) {
+ servers_prop = g_new(uint32_t, smt_threads * 2);
+ for (i = 0; i < smt_threads; i++) {
+ pnv_cc->get_pir_tir(chip, pc->hwid, i, &pir, NULL);
+ servers_prop[i * 2] = cpu_to_be32(pir);
+
+ pnv_cc->get_pir_tir(chip, pc->hwid + 1, i, &pir, NULL);
+ servers_prop[i * 2 + 1] = cpu_to_be32(pir);
+ }
+ _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
+ servers_prop, sizeof(*servers_prop) * smt_threads
+ * 2)));
+ } else {
+ servers_prop = g_new(uint32_t, smt_threads);
+ for (i = 0; i < smt_threads; i++) {
+ pnv_cc->get_pir_tir(chip, pc->hwid, i, &pir, NULL);
+ servers_prop[i] = cpu_to_be32(pir);
+ }
+ _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
+ servers_prop, sizeof(*servers_prop) * smt_threads)));
}
- _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
- servers_prop, sizeof(*servers_prop) * smt_threads)));
+ g_free(servers_prop);
return offset;
}
@@ -389,6 +408,10 @@ static void pnv_chip_power9_dt_populate(PnvChip *chip,
void *fdt)
_FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
pa_features_300, sizeof(pa_features_300))));
+
+ if (pnv_core->big_core) {
+ i++; /* Big-core groups two QEMU cores */
+ }
}
if (chip->ram_size) {
@@ -450,6 +473,10 @@ static void pnv_chip_power10_dt_populate(PnvChip *chip,
void *fdt)
_FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
pa_features_31, sizeof(pa_features_31))));
+
+ if (pnv_core->big_core) {
+ i++; /* Big-core groups two QEMU cores */
+ }
}
if (chip->ram_size) {
--
2.45.1
- [PATCH 06/18] ppc/pnv: specialise init for powernv8/9/10 machines, (continued)
- [PATCH 06/18] ppc/pnv: specialise init for powernv8/9/10 machines, Nicholas Piggin, 2024/07/11
- [PATCH 07/18] ppc/pnv: Extend chip_pir class method to TIR as well, Nicholas Piggin, 2024/07/11
- [PATCH 08/18] ppc: Add a core_index to CPUPPCState for SMT vCPUs, Nicholas Piggin, 2024/07/11
- [PATCH 10/18] ppc: Add has_smt_siblings property to CPUPPCState, Nicholas Piggin, 2024/07/11
- [PATCH 11/18] ppc/pnv: Add a big-core mode that joins two regular cores, Nicholas Piggin, 2024/07/11
- [PATCH 12/18] ppc/pnv: Add allow for big-core differences in DT generation,
Nicholas Piggin <=
- [PATCH 09/18] target/ppc: Add helpers to check for SMT sibling threads, Nicholas Piggin, 2024/07/11
- [PATCH 13/18] ppc/pnv: Implement big-core PVR for Power9/10, Nicholas Piggin, 2024/07/11
- [PATCH 14/18] ppc/pnv: Implement Power9 CPU core thread state indirect register, Nicholas Piggin, 2024/07/11
- [PATCH 15/18] ppc/pnv: Add POWER10 ChipTOD quirk for big-core, Nicholas Piggin, 2024/07/11
- [PATCH 16/18] ppc/pnv: Add big-core machine property, Nicholas Piggin, 2024/07/11
- [PATCH 18/18] ppc/pnv: Add an LPAR per core machine option, Nicholas Piggin, 2024/07/11
- [PATCH 17/18] ppc/pnv: Implement POWER10 PC xscom registers for direct controls, Nicholas Piggin, 2024/07/11
- Re: [PATCH 00/18] ppc/pnv: Better big-core model, lpar-per-core, PC unit, Cédric Le Goater, 2024/07/11