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[PATCH 15/18] ppc/pnv: Add POWER10 ChipTOD quirk for big-core
From: |
Nicholas Piggin |
Subject: |
[PATCH 15/18] ppc/pnv: Add POWER10 ChipTOD quirk for big-core |
Date: |
Fri, 12 Jul 2024 00:18:47 +1000 |
POWER10 has a quirk in its ChipTOD addressing that requires the even
small-core to be selected even when programming the odd small-core.
This allows skiboot chiptod init to run in big-core mode.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
include/hw/ppc/pnv.h | 1 +
include/hw/ppc/pnv_core.h | 7 +++++++
hw/ppc/pnv.c | 1 +
hw/ppc/pnv_core.c | 3 +++
target/ppc/timebase_helper.c | 9 +++++++++
5 files changed, 21 insertions(+)
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index 283ddd50e7..c56d152889 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -77,6 +77,7 @@ struct PnvMachineClass {
const char *compat;
int compat_size;
int max_smt_threads;
+ bool quirk_tb_big_core;
void (*dt_power_mgt)(PnvMachineState *pnv, void *fdt);
void (*i2c_init)(PnvMachineState *pnv);
diff --git a/include/hw/ppc/pnv_core.h b/include/hw/ppc/pnv_core.h
index 50164e9e1f..c8784777a4 100644
--- a/include/hw/ppc/pnv_core.h
+++ b/include/hw/ppc/pnv_core.h
@@ -27,6 +27,13 @@
/* Per-core ChipTOD / TimeBase state */
typedef struct PnvCoreTODState {
+ /*
+ * POWER10 DD2.0 - big core TFMR drives the state machine on the even
+ * small core. Skiboot has a workaround that targets the even small core
+ * for CHIPTOD_TO_TB ops.
+ */
+ bool big_core_quirk;
+
int tb_ready_for_tod; /* core TB ready to receive TOD from chiptod */
int tod_sent_to_tb; /* chiptod sent TOD to the core TB */
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index d7488be74c..efc9cf2cc3 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -2650,6 +2650,7 @@ static void pnv_machine_p10_common_class_init(ObjectClass
*oc, void *data)
pmc->compat = compat;
pmc->compat_size = sizeof(compat);
pmc->max_smt_threads = 4;
+ pmc->quirk_tb_big_core = true;
pmc->dt_power_mgt = pnv_dt_power_mgt;
xfc->match_nvt = pnv10_xive_match_nvt;
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index a96ec4e2b9..68cc5914c6 100644
--- a/hw/ppc/pnv_core.c
+++ b/hw/ppc/pnv_core.c
@@ -280,6 +280,7 @@ static void pnv_core_realize(DeviceState *dev, Error **errp)
PnvCore *pc = PNV_CORE(OBJECT(dev));
PnvCoreClass *pcc = PNV_CORE_GET_CLASS(pc);
CPUCore *cc = CPU_CORE(OBJECT(dev));
+ PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(pc->chip->pnv_machine);
const char *typename = pnv_core_cpu_typename(pc);
Error *local_err = NULL;
void *obj;
@@ -288,6 +289,8 @@ static void pnv_core_realize(DeviceState *dev, Error **errp)
assert(pc->chip);
+ pc->tod_state.big_core_quirk = pmc->quirk_tb_big_core;
+
pc->threads = g_new(PowerPCCPU *, cc->nr_threads);
for (i = 0; i < cc->nr_threads; i++) {
PowerPCCPU *cpu;
diff --git a/target/ppc/timebase_helper.c b/target/ppc/timebase_helper.c
index 44cacf065e..019b8ee41f 100644
--- a/target/ppc/timebase_helper.c
+++ b/target/ppc/timebase_helper.c
@@ -20,6 +20,7 @@
#include "cpu.h"
#include "hw/ppc/ppc.h"
#include "hw/ppc/pnv_core.h"
+#include "hw/ppc/pnv_chip.h"
#include "exec/helper-proto.h"
#include "exec/exec-all.h"
#include "qemu/log.h"
@@ -297,6 +298,14 @@ static PnvCoreTODState *cpu_get_tbst(PowerPCCPU *cpu)
{
PnvCore *pc = pnv_cpu_state(cpu)->pnv_core;
+ if (pc->big_core && pc->tod_state.big_core_quirk) {
+ /* Must operate on the even small core */
+ int core_id = CPU_CORE(pc)->core_id;
+ if (core_id & 1) {
+ pc = pc->chip->cores[core_id & ~1];
+ }
+ }
+
return &pc->tod_state;
}
--
2.45.1
- [PATCH 08/18] ppc: Add a core_index to CPUPPCState for SMT vCPUs, (continued)
- [PATCH 08/18] ppc: Add a core_index to CPUPPCState for SMT vCPUs, Nicholas Piggin, 2024/07/11
- [PATCH 10/18] ppc: Add has_smt_siblings property to CPUPPCState, Nicholas Piggin, 2024/07/11
- [PATCH 11/18] ppc/pnv: Add a big-core mode that joins two regular cores, Nicholas Piggin, 2024/07/11
- [PATCH 12/18] ppc/pnv: Add allow for big-core differences in DT generation, Nicholas Piggin, 2024/07/11
- [PATCH 09/18] target/ppc: Add helpers to check for SMT sibling threads, Nicholas Piggin, 2024/07/11
- [PATCH 13/18] ppc/pnv: Implement big-core PVR for Power9/10, Nicholas Piggin, 2024/07/11
- [PATCH 14/18] ppc/pnv: Implement Power9 CPU core thread state indirect register, Nicholas Piggin, 2024/07/11
- [PATCH 15/18] ppc/pnv: Add POWER10 ChipTOD quirk for big-core,
Nicholas Piggin <=
- [PATCH 16/18] ppc/pnv: Add big-core machine property, Nicholas Piggin, 2024/07/11
- [PATCH 18/18] ppc/pnv: Add an LPAR per core machine option, Nicholas Piggin, 2024/07/11
- [PATCH 17/18] ppc/pnv: Implement POWER10 PC xscom registers for direct controls, Nicholas Piggin, 2024/07/11
- Re: [PATCH 00/18] ppc/pnv: Better big-core model, lpar-per-core, PC unit, Cédric Le Goater, 2024/07/11