Re: [PATCH v4 03/11] target/riscv: Add zcmop extension

[Jim Shu]

On Tue, Jul 9, 2024 at 7:40 PM LIU Zhiwei <zhiwei_liu@linux.alibaba.com> wrote:
>
> Zcmop defines eight 16-bit MOP instructions named C.MOP.n, where n is
> an odd integer between 1 and 15, inclusive. C.MOP.n is encoded in
> the reserved encoding space corresponding to C.LUI xn, 0.
>
> Unlike the MOPs defined in the Zimop extension, the C.MOP.n instructions
> are defined to not write any register.
>
> In current implementation, C.MOP.n only has an check function, without any
> other more behavior.
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> Reviewed-by: Deepak Gupta <debug@rivosinc.com>
> ---
>  target/riscv/cpu.c                          |  2 ++
>  target/riscv/cpu_cfg.h                      |  1 +
>  target/riscv/insn16.decode                  |  1 +
>  target/riscv/insn_trans/trans_rvzcmop.c.inc | 29 +++++++++++++++++++++
>  target/riscv/tcg/tcg-cpu.c                  |  5 ++++
>  target/riscv/translate.c                    |  1 +
>  6 files changed, 39 insertions(+)
>  create mode 100644 target/riscv/insn_trans/trans_rvzcmop.c.inc
>

Reviewed-by: Jim Shu <jim.shu@sifive.com>