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Re: [PATCH v4 04/11] disas/riscv: Support zcmop disassemble
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From: |
Jim Shu |
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Subject: |
Re: [PATCH v4 04/11] disas/riscv: Support zcmop disassemble |
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Date: |
Fri, 12 Jul 2024 17:08:06 +0800 |
On Tue, Jul 9, 2024 at 7:41 PM LIU Zhiwei <zhiwei_liu@linux.alibaba.com> wrote:
>
> Although in QEMU disassemble, we usually lift compressed instruction
> to an normal format when display the instruction name. For C.MOP.n,
> it is more reasonable to directly display its compressed name, because
> its behavior can be redefined by later extension.
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
> Acked-by: Alistair Francis <alistair.francis@wdc.com>
> Reviewed-by: Deepak Gupta <debug@rivosinc.com>
> ---
> disas/riscv.c | 23 +++++++++++++++++++++++
> 1 file changed, 23 insertions(+)
Reviewed-by: Jim Shu <jim.shu@sifive.com>
- [PATCH v4 00/11] target/riscv: Support zimop/zcmop/zama16b/zabha, LIU Zhiwei, 2024/07/09
- [PATCH v4 01/11] target/riscv: Add zimop extension, LIU Zhiwei, 2024/07/09
- [PATCH v4 02/11] disas/riscv: Support zimop disassemble, LIU Zhiwei, 2024/07/09
- [PATCH v4 03/11] target/riscv: Add zcmop extension, LIU Zhiwei, 2024/07/09
- [PATCH v4 04/11] disas/riscv: Support zcmop disassemble, LIU Zhiwei, 2024/07/09
- Re: [PATCH v4 04/11] disas/riscv: Support zcmop disassemble,
Jim Shu <=
- [PATCH v4 05/11] target/riscv: Support Zama16b extension, LIU Zhiwei, 2024/07/09
- [PATCH v4 06/11] target/riscv: Move gen_amo before implement Zabha, LIU Zhiwei, 2024/07/09
- [PATCH v4 07/11] target/riscv: Add AMO instructions for Zabha, LIU Zhiwei, 2024/07/09
- [PATCH v4 08/11] target/riscv: Move gen_cmpxchg before adding amocas.[b|h], LIU Zhiwei, 2024/07/09
- [PATCH v4 09/11] target/riscv: Add amocas.[b|h] for Zabha, LIU Zhiwei, 2024/07/09
- [PATCH v4 10/11] target/riscv: Expose zabha extension as a cpu property, LIU Zhiwei, 2024/07/09
- [PATCH v4 11/11] disas/riscv: Support zabha disassemble, LIU Zhiwei, 2024/07/09
- Re: [PATCH v4 00/11] target/riscv: Support zimop/zcmop/zama16b/zabha, Alistair Francis, 2024/07/09