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Re: [PATCH v5 10/13] hw/acpi: Generic Port Affinity Structure support


From: Jonathan Cameron
Subject: Re: [PATCH v5 10/13] hw/acpi: Generic Port Affinity Structure support
Date: Wed, 17 Jul 2024 16:40:30 +0100

On Wed, 17 Jul 2024 11:11:06 -0400
"Michael S. Tsirkin" <mst@redhat.com> wrote:

> On Wed, Jul 17, 2024 at 04:02:58PM +0100, Jonathan Cameron wrote:
> > On Mon, 15 Jul 2024 16:48:41 +0200
> > Igor Mammedov <imammedo@redhat.com> wrote:
> >   
> > > On Fri, 12 Jul 2024 12:08:14 +0100
> > > Jonathan Cameron <Jonathan.Cameron@huawei.com> wrote:
> > >   
> > > > These are very similar to the recently added Generic Initiators
> > > > but instead of representing an initiator of memory traffic they
> > > > represent an edge point beyond which may lie either targets or
> > > > initiators.  Here we add these ports such that they may
> > > > be targets of hmat_lb records to describe the latency and
> > > > bandwidth from host side initiators to the port.  A discoverable
> > > > mechanism such as UEFI CDAT read from CXL devices and switches
> > > > is used to discover the remainder of the path, and the OS can build
> > > > up full latency and bandwidth numbers as need for work and data
> > > > placement decisions.
> > > > 
> > > > Acked-by: Markus Armbruster <armbru@redhat.com>
> > > > Tested-by: "Huang, Ying" <ying.huang@intel.com>
> > > > Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>    
> > > 
> > > ACPI tables generation LGTM
> > > As for the rest my review is perfunctory mostly.  
> > 
> > The node type points and missing descriptor applying equally to generic
> > initiators. I'll add a couple of patches cleaning that up as well as 
> > fixing them up for generic ports.
> > 
> > For the exit(1) that was copying other similar locations. I don't
> > mind changing it though if something else is preferred.
> > 
> > Given tight timescales (and I was away for a few days which didn't
> > help), I'll send out a v6 with changes as below.
> > 
> > Jonathan
> >   
> 
> I'm working on a pull and going offline for a week guys, what's not in
> will be in the next release.  Sorry.

No problem. Thanks for letting us know!

In that case I'll sit on v6 for a while and hopefully we can get it
lined up early next cycle without too much bios-tables test churn pain.

Jonathan



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