Re: [PATCH] docs: add more information about CXL2.0 device type

[Jonathan Cameron]

On Fri, 19 Jul 2024 12:57:33 +0800
luzhixing12345 <luzhixing12345@gmail.com> wrote:

> Add more information with CXL type1 and type2 devices.
> 
> Original doc says "May also have device private memory accessible 
> via means such as PCI memory reads and writes to BARs.", but actually
> CXL type1 devices doesn't have device memory.

Hi Luzhixing,

That's a missunderstanding. It contains no memory accesible via CXL.mem (so
host managed device memory) butit may contain memory accessible via CXL.IO etc.
Such memory is out of the scope of the CXL specification but the
intent of the text written here is to make it clear that
such memory can exist.

> 
> Signed-off-by: luzhixing12345 <luzhixing12345@gmail.com>
The name part of the SoB should be your name which I'm guessing
doesn't include numbers.

There seem to be additional changes in the text below.
I'm not sure what the purpose was?

> ---
>  docs/system/devices/cxl.rst | 18 ++++++------------
>  1 file changed, 6 insertions(+), 12 deletions(-)
> 
> diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst
> index 882b036f5e..ee50a3c18d 100644
> --- a/docs/system/devices/cxl.rst
> +++ b/docs/system/devices/cxl.rst
> @@ -46,20 +46,14 @@ CXL 2.0 Device Types
>  --------------------
>  CXL 2.0 End Points are often categorized into three types.
>  
> -**Type 1:** These support coherent caching of host memory.  Example might
> -be a crypto accelerators.  May also have device private memory accessible
> -via means such as PCI memory reads and writes to BARs.
> +**Type 1: Accelerators without device memory**. These support coherent 
> caching of host memory. Example might be a crypto accelerators or smart NICs 
> that use coherency semantics along with PCIe-style DMA transfers. Type1 
> devices implement a fully coherent cache but no host-managed device memory.

Needs to be wrapped.

>  
> -**Type 2:** These support coherent caching of host memory and host
> -managed device memory (HDM) for which the coherency protocol is managed
> -by the host. This is a complex topic, so for more information on CXL
> -coherency see the CXL 2.0 specification.
> +**Type 2: Accelerators with device memory**. These support coherent caching 
> of host memory and host managed device memory (HDM) for which the coherency 
> protocol is managed by the host. Type 2 devices are accelerators such as 
> GP-GPUs and FPGAs with device memory that can be mapped in part to the 
> cacheable system memory. These devices also cache system memory for 
> processing.
>  
> -**Type 3 Memory devices:**  These devices act as a means of attaching
> -additional memory (HDM) to a CXL host including both volatile and
> -persistent memory. The CXL topology may support interleaving across a
> -number of Type 3 memory devices using HDM Decoders in the host, host
> -bridge, switch upstream port and endpoints.
> +**Type 3: Memory devices**. These devices act as a means of attaching
> +additional memory (HDM) to a CXL host with different memory types,
Why make this change? What memory do you have that is neither persistent nor 
volatile?

> + including supporting multiple memory tiers attached to the device with both 
> volatile and persistent memory. The CXL topology may support interleaving 
> across a number of Type 3 memory devices using HDM Decoders in the host, host 
> bridge, switch upstream port and endpoints.
> +
> +See more information about CXL.io CXL.cache CXL.mem in the `CXL 2.0 
> specification 
> <https://computeexpresslink.org/past-cxl-specifications-landing-page/>`_.
>  
>  Scope of CXL emulation in QEMU
>  ------------------------------