qemu-devel
[Top][All Lists]
Advanced

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [PULL 26/30] target/riscv: Do not setup pmu timer if OF is disabled


From: Richard Henderson
Subject: Re: [PULL 26/30] target/riscv: Do not setup pmu timer if OF is disabled
Date: Tue, 23 Jul 2024 10:49:57 +1000
User-agent: Mozilla Thunderbird

On 7/23/24 10:43, Alistair Francis wrote:
#define get_field(reg, mask) (((reg) & \
                  (uint64_t)(mask)) / ((mask) & ~((mask) << 1)))

Notice that part of this expression is "(mask) << 1". So Coverity complains
that we took a constant value and shifted it right off the top.

I think this is probably a false positive, but why is target/riscv
using its own ad-hoc macros for extracting bitfields? We have
a standard set of extract/deposit macros in bitops.h, and not

Thanks for pointing those out. I checked the get_field usage from the
beginning of riscv support 6 years back.
There are tons of users of get_field in a bunch of riscv sources. I
guess it was just added once and everybody kept using it
without switching to generic functions.

I think you are right about that

I think this macro comes from spike, and it was copied in with a bunch of other basic isa defines at the start of the qemu port.


r~



reply via email to

[Prev in Thread] Current Thread [Next in Thread]