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Re: [PATCH v1 11/17] intel_iommu: Extract device IOTLB invalidation logi
From: |
CLEMENT MATHIEU--DRIF |
Subject: |
Re: [PATCH v1 11/17] intel_iommu: Extract device IOTLB invalidation logic |
Date: |
Wed, 24 Jul 2024 08:35:21 +0000 |
Hi Zhenzhong,
This patch has been merged into staging this morning, be careful when
re-sending your series.
Here is the link :
https://github.com/qemu/qemu/commit/6410f877f5ed535acd01bbfaa4baec379e44d0ef#diff-c19adbf518f644e9b651b67266802e14787292ab9d6cd4210b4f974585be6009
>cmd
On 18/07/2024 10:16, Zhenzhong Duan wrote:
> Caution: External email. Do not open attachments or click links, unless this
> email comes from a known sender and you know the content is safe.
>
>
> From: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com>
>
> This piece of code can be shared by both IOTLB invalidation and
> PASID-based IOTLB invalidation
>
> No functional changes intended.
>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Signed-off-by: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com>
> Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
> ---
> hw/i386/intel_iommu.c | 57 +++++++++++++++++++++++++------------------
> 1 file changed, 33 insertions(+), 24 deletions(-)
>
> diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
> index 8ebb6dbd7d..4d5a457f92 100644
> --- a/hw/i386/intel_iommu.c
> +++ b/hw/i386/intel_iommu.c
> @@ -2975,13 +2975,43 @@ static bool vtd_process_inv_iec_desc(IntelIOMMUState
> *s,
> return true;
> }
>
> +static void do_invalidate_device_tlb(VTDAddressSpace *vtd_dev_as,
> + bool size, hwaddr addr)
> +{
> + /*
> + * According to ATS spec table 2.4:
> + * S = 0, bits 15:12 = xxxx range size: 4K
> + * S = 1, bits 15:12 = xxx0 range size: 8K
> + * S = 1, bits 15:12 = xx01 range size: 16K
> + * S = 1, bits 15:12 = x011 range size: 32K
> + * S = 1, bits 15:12 = 0111 range size: 64K
> + * ...
> + */
> +
> + IOMMUTLBEvent event;
> + uint64_t sz;
> +
> + if (size) {
> + sz = (VTD_PAGE_SIZE * 2) << cto64(addr >> VTD_PAGE_SHIFT);
> + addr &= ~(sz - 1);
> + } else {
> + sz = VTD_PAGE_SIZE;
> + }
> +
> + event.type = IOMMU_NOTIFIER_DEVIOTLB_UNMAP;
> + event.entry.target_as = &vtd_dev_as->as;
> + event.entry.addr_mask = sz - 1;
> + event.entry.iova = addr;
> + event.entry.perm = IOMMU_NONE;
> + event.entry.translated_addr = 0;
> + memory_region_notify_iommu(&vtd_dev_as->iommu, 0, event);
> +}
> +
> static bool vtd_process_device_iotlb_desc(IntelIOMMUState *s,
> VTDInvDesc *inv_desc)
> {
> VTDAddressSpace *vtd_dev_as;
> - IOMMUTLBEvent event;
> hwaddr addr;
> - uint64_t sz;
> uint16_t sid;
> bool size;
>
> @@ -3006,28 +3036,7 @@ static bool
> vtd_process_device_iotlb_desc(IntelIOMMUState *s,
> goto done;
> }
>
> - /* According to ATS spec table 2.4:
> - * S = 0, bits 15:12 = xxxx range size: 4K
> - * S = 1, bits 15:12 = xxx0 range size: 8K
> - * S = 1, bits 15:12 = xx01 range size: 16K
> - * S = 1, bits 15:12 = x011 range size: 32K
> - * S = 1, bits 15:12 = 0111 range size: 64K
> - * ...
> - */
> - if (size) {
> - sz = (VTD_PAGE_SIZE * 2) << cto64(addr >> VTD_PAGE_SHIFT);
> - addr &= ~(sz - 1);
> - } else {
> - sz = VTD_PAGE_SIZE;
> - }
> -
> - event.type = IOMMU_NOTIFIER_DEVIOTLB_UNMAP;
> - event.entry.target_as = &vtd_dev_as->as;
> - event.entry.addr_mask = sz - 1;
> - event.entry.iova = addr;
> - event.entry.perm = IOMMU_NONE;
> - event.entry.translated_addr = 0;
> - memory_region_notify_iommu(&vtd_dev_as->iommu, 0, event);
> + do_invalidate_device_tlb(vtd_dev_as, size, addr);
>
> done:
> return true;
> --
> 2.34.1
>
- RE: [PATCH v1 04/17] intel_iommu: Flush stage-2 cache in PADID-selective PASID-based iotlb invalidation, (continued)
- [PATCH v1 05/17] intel_iommu: Rename slpte to pte, Zhenzhong Duan, 2024/07/18
- [PATCH v1 06/17] intel_iommu: Implement stage-1 translation, Zhenzhong Duan, 2024/07/18
- [PATCH v1 07/17] intel_iommu: Check if the input address is canonical, Zhenzhong Duan, 2024/07/18
- [PATCH v1 08/17] intel_iommu: Set accessed and dirty bits during first stage translation, Zhenzhong Duan, 2024/07/18
- [PATCH v1 09/17] intel_iommu: Flush stage-1 cache in iotlb invalidation, Zhenzhong Duan, 2024/07/18
- [PATCH v1 10/17] intel_iommu: Process PASID-based iotlb invalidation, Zhenzhong Duan, 2024/07/18
- [PATCH v1 11/17] intel_iommu: Extract device IOTLB invalidation logic, Zhenzhong Duan, 2024/07/18
- Re: [PATCH v1 11/17] intel_iommu: Extract device IOTLB invalidation logic,
CLEMENT MATHIEU--DRIF <=
- [PATCH v1 12/17] intel_iommu: Add an internal API to find an address space with PASID, Zhenzhong Duan, 2024/07/18
- [PATCH v1 13/17] intel_iommu: Add support for PASID-based device IOTLB invalidation, Zhenzhong Duan, 2024/07/18
- [PATCH v1 14/17] intel_iommu: piotlb invalidation should notify unmap, Zhenzhong Duan, 2024/07/18
[PATCH v1 15/17] intel_iommu: Set default aw_bits to 48 in scalable modren mode, Zhenzhong Duan, 2024/07/18