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[PATCH v6 5/5] ppc/pseries: Add Power11 cpu type
From: |
Aditya Gupta |
Subject: |
[PATCH v6 5/5] ppc/pseries: Add Power11 cpu type |
Date: |
Wed, 31 Jul 2024 00:53:25 +0530 |
Add sPAPR CPU Core definition for Power11
Cc: Cédric Le Goater <clg@kaod.org>
Cc: Daniel Henrique Barboza <danielhb413@gmail.com>
Cc: David Gibson <david@gibson.dropbear.id.au>
Cc: Frédéric Barrat <fbarrat@linux.ibm.com>
Cc: Harsh Prateek Bora <harshpb@linux.ibm.com>
Cc: Mahesh J Salgaonkar <mahesh@linux.ibm.com>
Cc: Madhavan Srinivasan <maddy@linux.ibm.com>
Cc: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
---
docs/system/ppc/pseries.rst | 17 +++++++++++++----
hw/ppc/spapr_cpu_core.c | 1 +
2 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/docs/system/ppc/pseries.rst b/docs/system/ppc/pseries.rst
index a876d897b6e4..bbc51aa7fcdb 100644
--- a/docs/system/ppc/pseries.rst
+++ b/docs/system/ppc/pseries.rst
@@ -14,10 +14,19 @@ virtualization capabilities.
Supported devices
=================
- * Multi processor support for many Power processors generations: POWER7,
- POWER7+, POWER8, POWER8NVL, POWER9, and Power10. Support for POWER5+ exists,
- but its state is unknown.
- * Interrupt Controller, XICS (POWER8) and XIVE (POWER9 and Power10)
+ * Multi processor support for many Power processors generations:
+ - POWER7, POWER7+
+ - POWER8, POWER8NVL
+ - POWER9
+ - Power10
+ - Power11
+ - Support for POWER5+ also exists, works with correct kernel/userspace
+ * Interrupt Controller
+ - XICS (POWER8)
+ - XIVE (Supported by below:)
+ - POWER9
+ - Power10
+ - Power11
* vPHB PCIe Host bridge.
* vscsi and vnet devices, compatible with the same devices available on a
PowerVM hypervisor with VIOS managing LPARs.
diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
index 56090abcd11a..347a1643ac7f 100644
--- a/hw/ppc/spapr_cpu_core.c
+++ b/hw/ppc/spapr_cpu_core.c
@@ -411,6 +411,7 @@ static const TypeInfo spapr_cpu_core_type_infos[] = {
DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"),
DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.2"),
DEFINE_SPAPR_CPU_CORE_TYPE("power10_v2.0"),
+ DEFINE_SPAPR_CPU_CORE_TYPE("power11_v2.0"),
#ifdef CONFIG_KVM
DEFINE_SPAPR_CPU_CORE_TYPE("host"),
#endif
--
2.45.2
- [PATCH v6 0/5] Power11 support for QEMU [PSeries], Aditya Gupta, 2024/07/30
- [PATCH v6 4/5] target/ppc: Add Power11 DD2.0 processor, Aditya Gupta, 2024/07/30
- [PATCH v6 2/5] target/ppc: Introduce 'PowerPCCPUClass::spapr_logical_pvr', Aditya Gupta, 2024/07/30
- [PATCH v6 3/5] target/ppc: Fix regression due to Power10 and Power11 having same PCR, Aditya Gupta, 2024/07/30
- [PATCH v6 5/5] ppc/pseries: Add Power11 cpu type,
Aditya Gupta <=
- [PATCH v6 1/5] target/ppc: Reduce code duplication across Power9/10 init code, Aditya Gupta, 2024/07/30
- Re: [PATCH v6 0/5] Power11 support for QEMU [PSeries], Nicholas Piggin, 2024/07/31