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Re: [PATCH v6 0/5] Power11 support for QEMU [PSeries]


From: Nicholas Piggin
Subject: Re: [PATCH v6 0/5] Power11 support for QEMU [PSeries]
Date: Wed, 31 Jul 2024 17:15:10 +1000

Hey Aditya,

Thanks for this, I think since we're past the hard freeze it may have
to wait until next release. If it was simply a new PRV maybe it could
be squeezed in, but since it has this PCR tangle then it's a bit
non-trivial. Apologies I didn't get to reviewing it earlier, will get
it in 9.2.

Thanks,
Nick

On Wed Jul 31, 2024 at 5:23 AM AEST, Aditya Gupta wrote:
> Overview
> ============
>
> Split "Power11 support for QEMU" into 2 patch series: pseries & powernv.
>
> This patch series is for pseries support for Power11.
>
> As Power11 core is same as Power10, hence much of the code has been reused 
> from
> Power10.
>
> Power11 was added in Linux in:
>   commit c2ed087ed35c ("powerpc: Add Power11 architected and raw mode")
>
> Git Tree for Testing
> ====================
>
> QEMU: https://github.com/adi-g15-ibm/qemu/tree/p11-v6-pseries
>
> Has been tested with following cases:
> * '-M pseries' / '-M pseries -cpu Power11'
> * '-smp' option tested
> * with compat mode: 'max-cpu-compat=power10' and 'max-cpu-compat=power9'
> * with/without device 'virtio-scsi-pci'
> * with/without -kernel and -drive with qcow_file
>
> Linux with Power11 support: https://github.com/torvalds/linux, since v6.9-rc1
>
> Changelog
> =========
> v6: 
>   + reorganised patches such that Power11 introduction is at end, and
>   cleanups and fixes is done before
>   + patch #1: renamed macros from POWER_* to PCC_*
>   + patch #2: rename 'logical_pvr' to 'spapr_logical_pvr' to better convey
>   the context
>
> v5:
>   + split patch series into pseries+powernv
>   + patch #1: apply harsh's patch to reduce duplication
>   + patch #2: simplified, by removing duplication
>   + patch #3: update docs, according to harsh's suggestion
>   + patch #4: no functional change, #define used for P9 & P10 pcr_supported
>   + patch #5: no change
>
> v4:
>   + patch #5: fix memory leak in pnv_chip_power10_quad_realize
>   - no change in other patches
>
> v3:
>   + patch #1: version power11 as power11_v2.0
>   + patch #2: split target hw/pseries code into patch #2
>   + patch #3,#4: fix regression due to Power10 and Power11 having same PCR
>   + patch #5: create pnv_chip_power11_dt_populate and split 
> pnv_chip_power10_common_realize as per review
>   + patch #6-#11: no change
>   - remove commit to make Power11 as default
>
> v2:
>   + split powernv patch into homer,lpc,occ,psi,sbe
>   + reduce code duplication by reusing power10 code
>   + make power11 as default
>   + rebase on qemu upstream/master
>   + add more information in commit descriptions
>   + update docs
>   + update skiboot.lid
>
>
> Aditya Gupta (4):
>   target/ppc: Introduce 'PowerPCCPUClass::spapr_logical_pvr'
>   target/ppc: Fix regression due to Power10 and Power11 having same PCR
>   target/ppc: Add Power11 DD2.0 processor
>   ppc/pseries: Add Power11 cpu type
>
> Harsh Prateek Bora (1):
>   target/ppc: Reduce code duplication across Power9/10 init code
>
>  docs/system/ppc/pseries.rst |  17 +++-
>  hw/ppc/spapr_cpu_core.c     |   1 +
>  target/ppc/compat.c         |  11 +++
>  target/ppc/cpu-models.c     |   3 +
>  target/ppc/cpu-models.h     |   3 +
>  target/ppc/cpu.h            |   3 +
>  target/ppc/cpu_init.c       | 188 +++++++++++++++---------------------
>  target/ppc/cpu_init.h       |  92 ++++++++++++++++++
>  8 files changed, 205 insertions(+), 113 deletions(-)
>  create mode 100644 target/ppc/cpu_init.h




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