Re: [PATCH-for-9.1 v2 2/2] hw/pci-host/gt64120: Set PCI base address register write mask

[Philippe Mathieu-Daudé]

On 1/8/24 16:56, Philippe Mathieu-Daudé wrote:
> When booting Linux we see:
>
>    PCI host bridge to bus 0000:00
>    pci_bus 0000:00: root bus resource [mem 0x10000000-0x17ffffff]
>    pci_bus 0000:00: root bus resource [io  0x1000-0x1fffff]
>    pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff]
>    pci 0000:00:00.0: [11ab:4620] type 00 class 0x060000
>    pci 0000:00:00.0: [Firmware Bug]: reg 0x14: invalid BAR (can't size)
>    pci 0000:00:00.0: [Firmware Bug]: reg 0x18: invalid BAR (can't size)
>    pci 0000:00:00.0: [Firmware Bug]: reg 0x1c: invalid BAR (can't size)
>    pci 0000:00:00.0: [Firmware Bug]: reg 0x20: invalid BAR (can't size)
>    pci 0000:00:00.0: [Firmware Bug]: reg 0x24: invalid BAR (can't size)
>
> This is due to missing base address register write mask.
> Add it to get:
>
>    PCI host bridge to bus 0000:00
>    pci_bus 0000:00: root bus resource [mem 0x10000000-0x17ffffff]
>    pci_bus 0000:00: root bus resource [io  0x1000-0x1fffff]
>    pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff]
>    pci 0000:00:00.0: [11ab:4620] type 00 class 0x060000
>    pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00000fff pref]
>    pci 0000:00:00.0: reg 0x14: [mem 0x01000000-0x01000fff pref]
>    pci 0000:00:00.0: reg 0x18: [mem 0x1c000000-0x1c000fff]
>    pci 0000:00:00.0: reg 0x1c: [mem 0x1f000000-0x1f000fff]
>    pci 0000:00:00.0: reg 0x20: [mem 0x1be00000-0x1be00fff]
>    pci 0000:00:00.0: reg 0x24: [io  0x14000000-0x14000007]
>
> Mention the datasheet referenced. Remove the "Malta assumptions ahead"
> comment since the reset values from the datasheet are used.

Argh this comment belongs to the previous patch :/

> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   hw/pci-host/gt64120.c | 7 +++++++
>   1 file changed, 7 insertions(+)