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[PULL 17/47] pci-ids.rst: add Red Hat pci-id for RISC-V IOMMU device
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From: |
Alistair Francis |
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Subject: |
[PULL 17/47] pci-ids.rst: add Red Hat pci-id for RISC-V IOMMU device |
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Date: |
Thu, 12 Sep 2024 15:29:22 +1000 |
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
The RISC-V IOMMU PCI device we're going to add next is a reference
implementation of the riscv-iommu spec [1], which predicts that the
IOMMU can be implemented as a PCIe device.
However, RISC-V International (RVI), the entity that ratified the
riscv-iommu spec, didn't bother assigning a PCI ID for this IOMMU PCIe
implementation that the spec predicts. This puts us in an uncommon
situation because we want to add the reference IOMMU PCIe implementation
but we don't have a PCI ID for it.
Given that RVI doesn't provide a PCI ID for it we reached out to Red Hat
and Gerd Hoffman, and they were kind enough to give us a PCI ID for the
RISC-V IOMMU PCI reference device.
Thanks Red Hat and Gerd for this RISC-V IOMMU PCIe device ID.
[1] https://github.com/riscv-non-isa/riscv-iommu/releases/tag/v1.0.0
Cc: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
Message-ID: <20240903201633.93182-5-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
docs/specs/pci-ids.rst | 2 ++
include/hw/pci/pci.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/docs/specs/pci-ids.rst b/docs/specs/pci-ids.rst
index 328ab31fe8..261b0f359f 100644
--- a/docs/specs/pci-ids.rst
+++ b/docs/specs/pci-ids.rst
@@ -98,6 +98,8 @@ PCI devices (other than virtio):
PCI ACPI ERST device (``-device acpi-erst``)
1b36:0013
PCI UFS device (``-device ufs``)
+1b36:0014
+ PCI RISC-V IOMMU device
All these devices are documented in :doc:`index`.
diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h
index eb26cac810..35d4fe0bbf 100644
--- a/include/hw/pci/pci.h
+++ b/include/hw/pci/pci.h
@@ -116,6 +116,7 @@ extern bool pci_available;
#define PCI_DEVICE_ID_REDHAT_PVPANIC 0x0011
#define PCI_DEVICE_ID_REDHAT_ACPI_ERST 0x0012
#define PCI_DEVICE_ID_REDHAT_UFS 0x0013
+#define PCI_DEVICE_ID_REDHAT_RISCV_IOMMU 0x0014
#define PCI_DEVICE_ID_REDHAT_QXL 0x0100
#define FMT_PCIBUS PRIx64
--
2.46.0
- [PULL 05/47] target/riscv/tcg/tcg-cpu.c: consider MISA bit choice in implied rule, (continued)
- [PULL 05/47] target/riscv/tcg/tcg-cpu.c: consider MISA bit choice in implied rule, Alistair Francis, 2024/09/12
- [PULL 07/47] target: riscv: Enable Bit Manip for OpenTitan Ibex CPU, Alistair Francis, 2024/09/12
- [PULL 08/47] target/riscv/kvm: Fix the group bit setting of AIA, Alistair Francis, 2024/09/12
- [PULL 09/47] target/riscv: Stop timer with infinite timecmp, Alistair Francis, 2024/09/12
- [PULL 10/47] target/riscv/cpu.c: Add 'fcsr' register to QEMU log as a part of F extension, Alistair Francis, 2024/09/12
- [PULL 11/47] util/util/cpuinfo-riscv.c: fix riscv64 build on musl libc, Alistair Francis, 2024/09/12
- [PULL 12/47] target/riscv: Preliminary textra trigger CSR writting support, Alistair Francis, 2024/09/12
- [PULL 13/47] target/riscv: Add textra matching condition for the triggers, Alistair Francis, 2024/09/12
- [PULL 14/47] exec/memtxattr: add process identifier to the transaction attributes, Alistair Francis, 2024/09/12
- [PULL 15/47] hw/riscv: add riscv-iommu-bits.h, Alistair Francis, 2024/09/12
- [PULL 17/47] pci-ids.rst: add Red Hat pci-id for RISC-V IOMMU device,
Alistair Francis <=
- [PULL 16/47] hw/riscv: add RISC-V IOMMU base emulation, Alistair Francis, 2024/09/12
- [PULL 18/47] hw/riscv: add riscv-iommu-pci reference device, Alistair Francis, 2024/09/12
- [PULL 19/47] hw/riscv/virt.c: support for RISC-V IOMMU PCIDevice hotplug, Alistair Francis, 2024/09/12
- [PULL 20/47] test/qtest: add riscv-iommu-pci tests, Alistair Francis, 2024/09/12
- [PULL 21/47] hw/riscv/riscv-iommu: add Address Translation Cache (IOATC), Alistair Francis, 2024/09/12
- [PULL 22/47] hw/riscv/riscv-iommu: add ATS support, Alistair Francis, 2024/09/12
- [PULL 26/47] bsd-user: Implement RISC-V CPU initialization and main loop, Alistair Francis, 2024/09/12
- [PULL 27/47] bsd-user: Add RISC-V CPU execution loop and syscall handling, Alistair Francis, 2024/09/12
- [PULL 23/47] hw/riscv/riscv-iommu: add DBG support, Alistair Francis, 2024/09/12