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[PULL 21/27] hw/net/can/xlnx-versal-canfd: Fix byte ordering
From: |
Peter Maydell |
Subject: |
[PULL 21/27] hw/net/can/xlnx-versal-canfd: Fix byte ordering |
Date: |
Fri, 13 Sep 2024 16:14:05 +0100 |
From: Doug Brown <doug@schmorgal.com>
The endianness of the CAN data was backwards in each group of 4 bytes.
For example, the following data:
00 11 22 33 44 55 66 77
was showing up like this:
33 22 11 00 77 66 55 44
Fix both the TX and RX code to put the data in the correct order.
Signed-off-by: Doug Brown <doug@schmorgal.com>
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
Acked-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
Message-id: 20240827034927.66659-6-doug@schmorgal.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/net/can/xlnx-versal-canfd.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/hw/net/can/xlnx-versal-canfd.c b/hw/net/can/xlnx-versal-canfd.c
index 9fba5b9dfc5..bcfffee1cc2 100644
--- a/hw/net/can/xlnx-versal-canfd.c
+++ b/hw/net/can/xlnx-versal-canfd.c
@@ -951,7 +951,7 @@ static void regs2frame(XlnxVersalCANFDState *s,
qemu_can_frame *frame,
}
for (j = 0; j < frame->can_dlc; j++) {
- val = 8 * i;
+ val = 8 * (3 - i);
frame->data[j] = extract32(s->regs[reg_num + 2 + (j / 4)], val, 8);
i++;
@@ -1093,19 +1093,19 @@ static void store_rx_sequential(XlnxVersalCANFDState *s,
case 0:
rx_reg_num = i / 4;
- data_reg_val = FIELD_DP32(0, RB_DW0_REGISTER, DATA_BYTES3,
+ data_reg_val = FIELD_DP32(0, RB_DW0_REGISTER, DATA_BYTES0,
frame->data[i]);
break;
case 1:
- data_reg_val |= FIELD_DP32(0, RB_DW0_REGISTER, DATA_BYTES2,
- frame->data[i]);
- break;
- case 2:
data_reg_val |= FIELD_DP32(0, RB_DW0_REGISTER, DATA_BYTES1,
frame->data[i]);
break;
+ case 2:
+ data_reg_val |= FIELD_DP32(0, RB_DW0_REGISTER, DATA_BYTES2,
+ frame->data[i]);
+ break;
case 3:
- data_reg_val |= FIELD_DP32(0, RB_DW0_REGISTER, DATA_BYTES0,
+ data_reg_val |= FIELD_DP32(0, RB_DW0_REGISTER, DATA_BYTES3,
frame->data[i]);
/*
* Last Bytes data which means we have all 4 bytes ready to
--
2.34.1
- [PULL 00/27] target-arm queue, Peter Maydell, 2024/09/13
- [PULL 01/27] hw/s390/ccw-device: Convert to three-phase reset, Peter Maydell, 2024/09/13
- [PULL 04/27] hw: Remove device_class_set_parent_reset(), Peter Maydell, 2024/09/13
- [PULL 05/27] target/alpha, hppa: Remove unused parent_reset fields, Peter Maydell, 2024/09/13
- [PULL 02/27] hw/s390/virtio-ccw: Convert to three-phase reset, Peter Maydell, 2024/09/13
- [PULL 03/27] target/s390: Convert CPU to Resettable interface, Peter Maydell, 2024/09/13
- [PULL 09/27] hw: Remove device_phases_reset(), Peter Maydell, 2024/09/13
- [PULL 13/27] hw/boards: Add hvf_get_physical_address_range to MachineClass, Peter Maydell, 2024/09/13
- [PULL 06/27] hw: Define new device_class_set_legacy_reset(), Peter Maydell, 2024/09/13
- [PULL 21/27] hw/net/can/xlnx-versal-canfd: Fix byte ordering,
Peter Maydell <=
- [PULL 24/27] MAINTAINERS: Remove Vikram Garhwal as maintainer, Peter Maydell, 2024/09/13
- [PULL 25/27] MAINTAINERS: Update Xilinx Versal OSPI maintainer's email address, Peter Maydell, 2024/09/13
- [PULL 17/27] hw/net/can/xlnx-versal-canfd: Fix interrupt level, Peter Maydell, 2024/09/13
- [PULL 16/27] target/arm/tcg: refine cache descriptions with a wrapper, Peter Maydell, 2024/09/13
- [PULL 08/27] hw: Rename DeviceClass::reset field to legacy_reset, Peter Maydell, 2024/09/13
- [PULL 23/27] hw/net/can/xlnx-versal-canfd: Fix FIFO issues, Peter Maydell, 2024/09/13
- [PULL 20/27] hw/net/can/xlnx-versal-canfd: Handle flags correctly, Peter Maydell, 2024/09/13
- [PULL 10/27] hw/core/qdev: Simplify legacy_reset handling, Peter Maydell, 2024/09/13
- [PULL 12/27] kvm: Use 'unsigned long' for request argument in functions wrapping ioctl(), Peter Maydell, 2024/09/13
- [PULL 18/27] hw/net/can/xlnx-versal-canfd: Fix CAN FD flag check, Peter Maydell, 2024/09/13