[PATCH 11/13] target/mips: Declare MXU registers as 32-bit

[Philippe Mathieu-Daudé]

MXU extension is only built for 32-bit targets,
so the MXU registers can be directly declared as
32-bit.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/mips/cpu.h               | 4 ++--
 target/mips/sysemu/machine.c    | 4 ++--
 target/mips/tcg/mxu_translate.c | 8 ++++----
 3 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index f6877ece8b4..f80b05885b1 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -514,8 +514,8 @@ struct TCState {
     float_status msa_fp_status;
 
 #define NUMBER_OF_MXU_REGISTERS 16
-    target_ulong mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1];
-    target_ulong mxu_cr;
+    uint32_t mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1];
+    uint32_t mxu_cr;
 #define MXU_CR_LC       31
 #define MXU_CR_RC       30
 #define MXU_CR_BIAS     2
diff --git a/target/mips/sysemu/machine.c b/target/mips/sysemu/machine.c
index 8af11fd896b..823a49e2ca1 100644
--- a/target/mips/sysemu/machine.c
+++ b/target/mips/sysemu/machine.c
@@ -98,8 +98,8 @@ static const VMStateField vmstate_tc_fields[] = {
     VMSTATE_INT32(CP0_Debug_tcstatus, TCState),
     VMSTATE_UINTTL(CP0_UserLocal, TCState),
     VMSTATE_INT32(msacsr, TCState),
-    VMSTATE_UINTTL_ARRAY(mxu_gpr, TCState, NUMBER_OF_MXU_REGISTERS - 1),
-    VMSTATE_UINTTL(mxu_cr, TCState),
+    VMSTATE_UINT32_ARRAY(mxu_gpr, TCState, NUMBER_OF_MXU_REGISTERS - 1),
+    VMSTATE_UINT32(mxu_cr, TCState),
     VMSTATE_END_OF_LIST()
 };
 
diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translate.c
index 20b8314b478..ee70ae96c32 100644
--- a/target/mips/tcg/mxu_translate.c
+++ b/target/mips/tcg/mxu_translate.c
@@ -606,8 +606,8 @@ enum {
 #define MXU_OPTN3_PTN7  7
 
 /* MXU registers */
-static TCGv mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1];
-static TCGv mxu_CR;
+static TCGv_i32 mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1];
+static TCGv_i32 mxu_CR;
 
 static const char mxuregnames[NUMBER_OF_MXU_REGISTERS][4] = {
     "XR1",  "XR2",  "XR3",  "XR4",  "XR5",  "XR6",  "XR7",  "XR8",
@@ -617,12 +617,12 @@ static const char mxuregnames[NUMBER_OF_MXU_REGISTERS][4] 
= {
 void mxu_translate_init(void)
 {
     for (unsigned i = 0; i < NUMBER_OF_MXU_REGISTERS - 1; i++) {
-        mxu_gpr[i] = tcg_global_mem_new(tcg_env,
+        mxu_gpr[i] = tcg_global_mem_new_i32(tcg_env,
                                         offsetof(CPUMIPSState, 
active_tc.mxu_gpr[i]),
                                         mxuregnames[i]);
     }
 
-    mxu_CR = tcg_global_mem_new(tcg_env,
+    mxu_CR = tcg_global_mem_new_i32(tcg_env,
                                 offsetof(CPUMIPSState, active_tc.mxu_cr),
                                 mxuregnames[NUMBER_OF_MXU_REGISTERS - 1]);
 }
-- 
2.45.2