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[PATCH 13/13] target/mips: Make DSPControl register 32-bit wide
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From: |
Philippe Mathieu-Daudé |
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Subject: |
[PATCH 13/13] target/mips: Make DSPControl register 32-bit wide |
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Date: |
Tue, 26 Nov 2024 14:15:45 +0100 |
Per 'MIPS® DSP Module for MIPS64™ Architecture, Revision 3.02',
* 3.10 Additional Register State for the DSP Module
~Figure 3.5 MIPS® DSP Module Control Register (DSPControl) Format~
the DSPControl register is 32-bit wide.
Convert it from 'target_ulong' to 'uint32_t'.
Update TCG calls to truncate/extend from i32 to target_ulong.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/mips/cpu.h | 2 +-
target/mips/tcg/sysemu_helper.h.inc | 4 +--
target/mips/sysemu/machine.c | 5 ++-
target/mips/tcg/dsp_helper.c | 10 +++---
target/mips/tcg/sysemu/cp0_helper.c | 4 +--
target/mips/tcg/translate.c | 40 +++++++++++++++++-------
target/mips/tcg/nanomips_translate.c.inc | 16 +++++++---
7 files changed, 54 insertions(+), 27 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index f80b05885b1..bc636510132 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -472,7 +472,7 @@ struct TCState {
target_ulong HI[MIPS_DSP_ACC];
target_ulong LO[MIPS_DSP_ACC];
target_ulong ACX[MIPS_DSP_ACC];
- target_ulong DSPControl;
+ uint32_t DSPControl;
int32_t CP0_TCStatus;
#define CP0TCSt_TCU3 31
#define CP0TCSt_TCU2 30
diff --git a/target/mips/tcg/sysemu_helper.h.inc
b/target/mips/tcg/sysemu_helper.h.inc
index 1861d538de1..36ce21f863b 100644
--- a/target/mips/tcg/sysemu_helper.h.inc
+++ b/target/mips/tcg/sysemu_helper.h.inc
@@ -144,12 +144,12 @@ DEF_HELPER_2(mftgpr, tl, env, i32)
DEF_HELPER_2(mftlo, tl, env, i32)
DEF_HELPER_2(mfthi, tl, env, i32)
DEF_HELPER_2(mftacx, tl, env, i32)
-DEF_HELPER_1(mftdsp, tl, env)
+DEF_HELPER_1(mftdsp, i32, env)
DEF_HELPER_3(mttgpr, void, env, tl, i32)
DEF_HELPER_3(mttlo, void, env, tl, i32)
DEF_HELPER_3(mtthi, void, env, tl, i32)
DEF_HELPER_3(mttacx, void, env, tl, i32)
-DEF_HELPER_2(mttdsp, void, env, tl)
+DEF_HELPER_2(mttdsp, void, env, i32)
DEF_HELPER_0(dmt, tl)
DEF_HELPER_0(emt, tl)
DEF_HELPER_1(dvpe, tl, env)
diff --git a/target/mips/sysemu/machine.c b/target/mips/sysemu/machine.c
index 823a49e2ca1..c1fb72864f6 100644
--- a/target/mips/sysemu/machine.c
+++ b/target/mips/sysemu/machine.c
@@ -88,7 +88,10 @@ static const VMStateField vmstate_tc_fields[] = {
VMSTATE_UINTTL_ARRAY(HI, TCState, MIPS_DSP_ACC),
VMSTATE_UINTTL_ARRAY(LO, TCState, MIPS_DSP_ACC),
VMSTATE_UINTTL_ARRAY(ACX, TCState, MIPS_DSP_ACC),
- VMSTATE_UINTTL(DSPControl, TCState),
+ VMSTATE_UINT32(DSPControl, TCState),
+#if defined(TARGET_MIPS64)
+ VMSTATE_UNUSED(4),
+#endif /* TARGET_MIPS64 */
VMSTATE_INT32(CP0_TCStatus, TCState),
VMSTATE_INT32(CP0_TCBind, TCState),
VMSTATE_UINTTL(CP0_TCHalt, TCState),
diff --git a/target/mips/tcg/dsp_helper.c b/target/mips/tcg/dsp_helper.c
index 7a4362c8ef4..e58d6b9ef84 100644
--- a/target/mips/tcg/dsp_helper.c
+++ b/target/mips/tcg/dsp_helper.c
@@ -54,7 +54,7 @@ typedef union {
static inline void set_DSPControl_overflow_flag(uint32_t flag, int position,
CPUMIPSState *env)
{
- env->active_tc.DSPControl |= (target_ulong)flag << position;
+ env->active_tc.DSPControl |= flag << position;
}
static inline void set_DSPControl_carryflag(bool flag, CPUMIPSState *env)
@@ -76,7 +76,7 @@ static inline void set_DSPControl_24(uint32_t flag, int len,
CPUMIPSState *env)
filter = ~filter;
env->active_tc.DSPControl &= filter;
- env->active_tc.DSPControl |= (target_ulong)flag << 24;
+ env->active_tc.DSPControl |= flag << 24;
}
static inline void set_DSPControl_pos(uint32_t pos, CPUMIPSState *env)
@@ -113,7 +113,7 @@ static inline uint32_t get_DSPControl_pos(CPUMIPSState *env)
static inline void set_DSPControl_efi(uint32_t flag, CPUMIPSState *env)
{
env->active_tc.DSPControl &= 0xFFFFBFFF;
- env->active_tc.DSPControl |= (target_ulong)flag << 14;
+ env->active_tc.DSPControl |= flag << 14;
}
#define DO_MIPS_SAT_ABS(size) \
@@ -2923,7 +2923,7 @@ target_ulong helper_##name(CPUMIPSState *env,
target_ulong rs, \
uint32_t pos, size, msb, lsb; \
uint32_t const sizefilter = 0x3F; \
target_ulong temp; \
- target_ulong dspc; \
+ uint32_t dspc; \
\
dspc = env->active_tc.DSPControl; \
\
@@ -3063,7 +3063,7 @@ target_ulong helper_##name(target_ulong rs, target_ulong
rt, \
{ \
uint32_t rs_t, rt_t; \
uint32_t cc; \
- target_ulong dsp; \
+ uint32_t dsp; \
int i; \
target_ulong result = 0; \
\
diff --git a/target/mips/tcg/sysemu/cp0_helper.c
b/target/mips/tcg/sysemu/cp0_helper.c
index 79a5c833cee..61b7644f3a4 100644
--- a/target/mips/tcg/sysemu/cp0_helper.c
+++ b/target/mips/tcg/sysemu/cp0_helper.c
@@ -1483,7 +1483,7 @@ target_ulong helper_mftacx(CPUMIPSState *env, uint32_t
sel)
}
}
-target_ulong helper_mftdsp(CPUMIPSState *env)
+uint32_t helper_mftdsp(CPUMIPSState *env)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
@@ -1543,7 +1543,7 @@ void helper_mttacx(CPUMIPSState *env, target_ulong arg1,
uint32_t sel)
}
}
-void helper_mttdsp(CPUMIPSState *env, target_ulong arg1)
+void helper_mttdsp(CPUMIPSState *env, uint32_t arg1)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index d6be37d56d3..6f2eacbba97 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -1172,7 +1172,8 @@ TCGv cpu_gpr[32], cpu_PC;
*/
TCGv_i64 cpu_gpr_hi[32];
TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];
-static TCGv cpu_dspctrl, btarget;
+static TCGv_i32 cpu_dspctrl;
+static TCGv btarget;
TCGv bcond;
static TCGv cpu_lladdr, cpu_llval;
static TCGv_i32 hflags;
@@ -4438,9 +4439,11 @@ static void gen_compute_branch(DisasContext *ctx,
uint32_t opc,
case OPC_BPOSGE32:
#if defined(TARGET_MIPS64)
case OPC_BPOSGE64:
- tcg_gen_andi_tl(t0, cpu_dspctrl, 0x7F);
+ tcg_gen_extu_i32_tl(t1, cpu_dspctrl);
+ tcg_gen_andi_tl(t0, t1, 0x7F);
#else
- tcg_gen_andi_tl(t0, cpu_dspctrl, 0x3F);
+ tcg_gen_extu_i32_tl(t1, cpu_dspctrl);
+ tcg_gen_andi_tl(t0, t1, 0x3F);
#endif
bcond_compute = 1;
btgt = ctx->base.pc_next + insn_bytes + offset;
@@ -8225,6 +8228,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext
*ctx, int rt, int rd,
gen_mfc0(ctx, t0, rt, sel);
}
} else {
+ TCGv_i32 t32;
switch (sel) {
/* GPR registers. */
case 0:
@@ -8270,7 +8274,9 @@ static void gen_mftr(CPUMIPSState *env, DisasContext
*ctx, int rt, int rd,
gen_helper_1e0i(mftacx, t0, 3);
break;
case 16:
- gen_helper_mftdsp(t0, tcg_env);
+ t32 = tcg_temp_new_i32();
+ gen_helper_mftdsp(t32, tcg_env);
+ tcg_gen_extu_i32_tl(t0, t32);
break;
default:
goto die;
@@ -8425,6 +8431,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext
*ctx, int rd, int rt,
gen_mtc0(ctx, t0, rd, sel);
}
} else {
+ TCGv_i32 t32;
switch (sel) {
/* GPR registers. */
case 0:
@@ -8470,7 +8477,9 @@ static void gen_mttr(CPUMIPSState *env, DisasContext
*ctx, int rd, int rt,
gen_helper_0e1i(mttacx, t0, 3);
break;
case 16:
- gen_helper_mttdsp(tcg_env, t0);
+ t32 = tcg_temp_new_i32();
+ gen_load_gpr_i32(t32, rt);
+ gen_helper_mttdsp(tcg_env, t32);
break;
default:
goto die;
@@ -12516,6 +12525,7 @@ static void gen_mipsdsp_add_cmp_pick(DisasContext *ctx,
TCGv t1;
TCGv v1_t;
TCGv v2_t;
+ TCGv_i32 t32;
if ((ret == 0) && (check_ret == 1)) {
/* Treat as NOP. */
@@ -12560,25 +12570,31 @@ static void gen_mipsdsp_add_cmp_pick(DisasContext
*ctx,
check_dsp_r2(ctx);
gen_helper_cmpgu_eq_qb(t1, v1_t, v2_t);
tcg_gen_mov_tl(cpu_gpr[ret], t1);
- tcg_gen_andi_tl(cpu_dspctrl, cpu_dspctrl, 0xF0FFFFFF);
+ tcg_gen_andi_i32(cpu_dspctrl, cpu_dspctrl, 0xF0FFFFFF);
tcg_gen_shli_tl(t1, t1, 24);
- tcg_gen_or_tl(cpu_dspctrl, cpu_dspctrl, t1);
+ t32 = tcg_temp_new_i32();
+ tcg_gen_trunc_tl_i32(t32, t1);
+ tcg_gen_or_i32(cpu_dspctrl, cpu_dspctrl, t32);
break;
case OPC_CMPGDU_LT_QB:
check_dsp_r2(ctx);
gen_helper_cmpgu_lt_qb(t1, v1_t, v2_t);
tcg_gen_mov_tl(cpu_gpr[ret], t1);
- tcg_gen_andi_tl(cpu_dspctrl, cpu_dspctrl, 0xF0FFFFFF);
+ tcg_gen_andi_i32(cpu_dspctrl, cpu_dspctrl, 0xF0FFFFFF);
tcg_gen_shli_tl(t1, t1, 24);
- tcg_gen_or_tl(cpu_dspctrl, cpu_dspctrl, t1);
+ t32 = tcg_temp_new_i32();
+ tcg_gen_trunc_tl_i32(t32, t1);
+ tcg_gen_or_i32(cpu_dspctrl, cpu_dspctrl, t32);
break;
case OPC_CMPGDU_LE_QB:
check_dsp_r2(ctx);
gen_helper_cmpgu_le_qb(t1, v1_t, v2_t);
tcg_gen_mov_tl(cpu_gpr[ret], t1);
- tcg_gen_andi_tl(cpu_dspctrl, cpu_dspctrl, 0xF0FFFFFF);
+ tcg_gen_andi_i32(cpu_dspctrl, cpu_dspctrl, 0xF0FFFFFF);
tcg_gen_shli_tl(t1, t1, 24);
- tcg_gen_or_tl(cpu_dspctrl, cpu_dspctrl, t1);
+ t32 = tcg_temp_new_i32();
+ tcg_gen_trunc_tl_i32(t32, t1);
+ tcg_gen_or_i32(cpu_dspctrl, cpu_dspctrl, t32);
break;
case OPC_CMP_EQ_PH:
check_dsp(ctx);
@@ -15303,7 +15319,7 @@ void mips_tcg_init(void)
offsetof(CPUMIPSState, active_tc.LO[i]),
regnames_LO[i]);
}
- cpu_dspctrl = tcg_global_mem_new(tcg_env,
+ cpu_dspctrl = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUMIPSState,
active_tc.DSPControl),
"DSPControl");
diff --git a/target/mips/tcg/nanomips_translate.c.inc
b/target/mips/tcg/nanomips_translate.c.inc
index 2ad936c66d4..1d6b70083b0 100644
--- a/target/mips/tcg/nanomips_translate.c.inc
+++ b/target/mips/tcg/nanomips_translate.c.inc
@@ -1136,7 +1136,8 @@ static void gen_compute_branch_nm(DisasContext *ctx,
uint32_t opc,
btgt = ctx->base.pc_next + insn_bytes + offset;
break;
case OPC_BPOSGE32:
- tcg_gen_andi_tl(t0, cpu_dspctrl, 0x3F);
+ tcg_gen_extu_i32_tl(t1, cpu_dspctrl);
+ tcg_gen_andi_tl(t0, t1, 0x3F);
bcond_compute = 1;
btgt = ctx->base.pc_next + insn_bytes + offset;
break;
@@ -3009,6 +3010,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx,
int opc,
TCGv t0 = tcg_temp_new();
TCGv v1_t = tcg_temp_new();
TCGv v2_t = tcg_temp_new();
+ TCGv_i32 v1_t32;
gen_load_gpr_tl(v1_t, rs);
gen_load_gpr_tl(v2_t, rt);
@@ -3056,19 +3058,25 @@ static void gen_pool32a5_nanomips_insn(DisasContext
*ctx, int opc,
case NM_CMPGDU_EQ_QB:
check_dsp_r2(ctx);
gen_helper_cmpgu_eq_qb(v1_t, v1_t, v2_t);
- tcg_gen_deposit_tl(cpu_dspctrl, cpu_dspctrl, v1_t, 24, 4);
+ v1_t32 = tcg_temp_new_i32();
+ tcg_gen_trunc_tl_i32(v1_t32, v1_t);
+ tcg_gen_deposit_i32(cpu_dspctrl, cpu_dspctrl, v1_t32, 24, 4);
gen_store_gpr_tl(v1_t, ret);
break;
case NM_CMPGDU_LT_QB:
check_dsp_r2(ctx);
gen_helper_cmpgu_lt_qb(v1_t, v1_t, v2_t);
- tcg_gen_deposit_tl(cpu_dspctrl, cpu_dspctrl, v1_t, 24, 4);
+ v1_t32 = tcg_temp_new_i32();
+ tcg_gen_trunc_tl_i32(v1_t32, v1_t);
+ tcg_gen_deposit_i32(cpu_dspctrl, cpu_dspctrl, v1_t32, 24, 4);
gen_store_gpr_tl(v1_t, ret);
break;
case NM_CMPGDU_LE_QB:
check_dsp_r2(ctx);
gen_helper_cmpgu_le_qb(v1_t, v1_t, v2_t);
- tcg_gen_deposit_tl(cpu_dspctrl, cpu_dspctrl, v1_t, 24, 4);
+ v1_t32 = tcg_temp_new_i32();
+ tcg_gen_trunc_tl_i32(v1_t32, v1_t);
+ tcg_gen_deposit_i32(cpu_dspctrl, cpu_dspctrl, v1_t32, 24, 4);
gen_store_gpr_tl(v1_t, ret);
break;
case NM_PACKRL_PH:
--
2.45.2