On Sun, 1 Dec 2024 at 15:11, Richard Henderson
<richard.henderson@linaro.org> wrote:
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 24 ++++++------------------
target/arm/tcg/a64.decode | 3 +++
2 files changed, 9 insertions(+), 18 deletions(-)
@@ -8661,21 +8664,6 @@ static void disas_fp_1src(DisasContext *s, uint32_t insn)
break;
case 0x6:
- switch (type) {
- case 1: /* BFCVT */
Here we decode BFCVT when the 'ftype' field (bits [23:22]) is 0b01...
- if (!dc_isar_feature(aa64_bf16, s)) {
- goto do_unallocated;
- }
- if (!fp_access_check(s)) {
- return;
- }
- handle_fp_1src_single(s, opcode, rd, rn);
- break;
- default:
- goto do_unallocated;
- }
- break;
-
default:
do_unallocated:
unallocated_encoding(s);
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index fbfdf96eb3..476989c1b4 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -45,6 +45,7 @@
&qrrrr_e q rd rn rm ra esz
@rr_h ........ ... ..... ...... rn:5 rd:5 &rr_e esz=1
+@rr_s ........ ... ..... ...... rn:5 rd:5 &rr_e esz=2
@rr_d ........ ... ..... ...... rn:5 rd:5 &rr_e esz=3
@rr_sd ........ ... ..... ...... rn:5 rd:5 &rr_e esz=%esz_sd
@rr_hsd ........ ... ..... ...... rn:5 rd:5 &rr_e esz=%esz_hsd
@@ -1337,6 +1338,8 @@ FRINTA_s 00011110 .. 1 001100 10000 ..... .....
@rr_hsd
FRINTX_s 00011110 .. 1 001110 10000 ..... ..... @rr_hsd
FRINTI_s 00011110 .. 1 001111 10000 ..... ..... @rr_hsd
+BFCVT_s 00011110 10 1 000110 10000 ..... ..... @rr_s
...but this decode pattern has them as 0b10.
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -1338,7 +1338,7 @@ FRINTA_s 00011110 .. 1 001100 10000 .....
..... @rr_hsd
FRINTX_s 00011110 .. 1 001110 10000 ..... ..... @rr_hsd
FRINTI_s 00011110 .. 1 001111 10000 ..... ..... @rr_hsd
-BFCVT_s 00011110 10 1 000110 10000 ..... ..... @rr_s
+BFCVT_s 00011110 01 1 000110 10000 ..... ..... @rr_s
# Floating-point Immediate
should fix this.