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[PATCH v6 07/20] intel_iommu: Check if the input address is canonical
From: |
Zhenzhong Duan |
Subject: |
[PATCH v6 07/20] intel_iommu: Check if the input address is canonical |
Date: |
Thu, 12 Dec 2024 16:37:44 +0800 |
From: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com>
Stage-1 translation must fail if the address to translate is
not canonical.
Signed-off-by: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Reviewed-by: Yi Liu <yi.l.liu@intel.com>
---
hw/i386/intel_iommu_internal.h | 1 +
hw/i386/intel_iommu.c | 23 +++++++++++++++++++++++
2 files changed, 24 insertions(+)
diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
index 86d3354198..3e7365dfff 100644
--- a/hw/i386/intel_iommu_internal.h
+++ b/hw/i386/intel_iommu_internal.h
@@ -326,6 +326,7 @@ typedef enum VTDFaultReason {
/* Non-zero reserved field in present first-stage paging entry */
VTD_FR_FS_PAGING_ENTRY_RSVD = 0x72,
VTD_FR_PASID_ENTRY_FSPTPTR_INV = 0x73, /* Invalid FSPTPTR in PASID entry */
+ VTD_FR_FS_NON_CANONICAL = 0x80, /* SNG.1 : Address for FS not canonical.*/
VTD_FR_FS_PAGING_ENTRY_US = 0x81, /* Privilege violation */
VTD_FR_SM_WRITE = 0x85, /* No write permission */
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index dbfd48fb65..a4a2a44f92 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -1824,6 +1824,7 @@ static const bool vtd_qualified_faults[] = {
[VTD_FR_FS_PAGING_ENTRY_P] = true,
[VTD_FR_FS_PAGING_ENTRY_RSVD] = true,
[VTD_FR_PASID_ENTRY_FSPTPTR_INV] = true,
+ [VTD_FR_FS_NON_CANONICAL] = true,
[VTD_FR_FS_PAGING_ENTRY_US] = true,
[VTD_FR_SM_WRITE] = true,
[VTD_FR_SM_INTERRUPT_ADDR] = true,
@@ -1930,6 +1931,22 @@ static inline bool vtd_flpte_present(uint64_t flpte)
return !!(flpte & VTD_FL_P);
}
+/* Return true if IOVA is canonical, otherwise false. */
+static bool vtd_iova_fl_check_canonical(IntelIOMMUState *s, uint64_t iova,
+ VTDContextEntry *ce, uint32_t pasid)
+{
+ uint64_t iova_limit = vtd_iova_limit(s, ce, s->aw_bits, pasid);
+ uint64_t upper_bits_mask = ~(iova_limit - 1);
+ uint64_t upper_bits = iova & upper_bits_mask;
+ bool msb = ((iova & (iova_limit >> 1)) != 0);
+
+ if (msb) {
+ return upper_bits == upper_bits_mask;
+ } else {
+ return !upper_bits;
+ }
+}
+
/*
* Given the @iova, get relevant @flptep. @flpte_level will be the last level
* of the translation, can be used for deciding the size of large page.
@@ -1945,6 +1962,12 @@ static int vtd_iova_to_flpte(IntelIOMMUState *s,
VTDContextEntry *ce,
uint32_t offset;
uint64_t flpte;
+ if (!vtd_iova_fl_check_canonical(s, iova, ce, pasid)) {
+ error_report_once("%s: detected non canonical IOVA (iova=0x%" PRIx64
","
+ "pasid=0x%" PRIx32 ")", __func__, iova, pasid);
+ return -VTD_FR_FS_NON_CANONICAL;
+ }
+
while (true) {
offset = vtd_iova_level_offset(iova, level);
flpte = vtd_get_pte(addr, offset);
--
2.34.1
- [PATCH v6 00/20] intel_iommu: Enable stage-1 translation for emulated device, Zhenzhong Duan, 2024/12/12
- [PATCH v6 01/20] intel_iommu: Use the latest fault reasons defined by spec, Zhenzhong Duan, 2024/12/12
- [PATCH v6 02/20] intel_iommu: Make pasid entry type check accurate, Zhenzhong Duan, 2024/12/12
- [PATCH v6 03/20] intel_iommu: Add a placeholder variable for scalable mode stage-1 translation, Zhenzhong Duan, 2024/12/12
- [PATCH v6 04/20] intel_iommu: Flush stage-2 cache in PASID-selective PASID-based iotlb invalidation, Zhenzhong Duan, 2024/12/12
- [PATCH v6 05/20] intel_iommu: Rename slpte to pte, Zhenzhong Duan, 2024/12/12
- [PATCH v6 06/20] intel_iommu: Implement stage-1 translation, Zhenzhong Duan, 2024/12/12
- [PATCH v6 07/20] intel_iommu: Check if the input address is canonical,
Zhenzhong Duan <=
- [PATCH v6 09/20] intel_iommu: Set accessed and dirty bits during stage-1 translation, Zhenzhong Duan, 2024/12/12
- [PATCH v6 08/20] intel_iommu: Check stage-1 translation result with interrupt range, Zhenzhong Duan, 2024/12/12
- [PATCH v6 10/20] intel_iommu: Flush stage-1 cache in iotlb invalidation, Zhenzhong Duan, 2024/12/12
- [PATCH v6 12/20] intel_iommu: Add an internal API to find an address space with PASID, Zhenzhong Duan, 2024/12/12
- [PATCH v6 14/20] intel_iommu: piotlb invalidation should notify unmap, Zhenzhong Duan, 2024/12/12
- [PATCH v6 11/20] intel_iommu: Process PASID-based iotlb invalidation, Zhenzhong Duan, 2024/12/12
- [PATCH v6 13/20] intel_iommu: Add support for PASID-based device IOTLB invalidation, Zhenzhong Duan, 2024/12/12
- [PATCH v6 16/20] intel_iommu: Set default aw_bits to 48 starting from QEMU 9.2, Zhenzhong Duan, 2024/12/12
- [PATCH v6 15/20] tests/acpi: q35: allow DMAR acpi table changes, Zhenzhong Duan, 2024/12/12
- [PATCH v6 17/20] tests/acpi: q35: Update host address width in DMAR, Zhenzhong Duan, 2024/12/12