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[PATCH v6 11/20] intel_iommu: Process PASID-based iotlb invalidation
From: |
Zhenzhong Duan |
Subject: |
[PATCH v6 11/20] intel_iommu: Process PASID-based iotlb invalidation |
Date: |
Thu, 12 Dec 2024 16:37:48 +0800 |
PASID-based iotlb (piotlb) is used during walking Intel
VT-d stage-1 page table.
This emulates the stage-1 page table iotlb invalidation requested
by a PASID-based IOTLB Invalidate Descriptor (P_IOTLB).
Signed-off-by: Yi Liu <yi.l.liu@intel.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Reviewed-by: Yi Liu <yi.l.liu@intel.com>
---
hw/i386/intel_iommu_internal.h | 3 +++
hw/i386/intel_iommu.c | 43 ++++++++++++++++++++++++++++++++++
2 files changed, 46 insertions(+)
diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
index 22dd3faf0c..5e4e563e62 100644
--- a/hw/i386/intel_iommu_internal.h
+++ b/hw/i386/intel_iommu_internal.h
@@ -471,6 +471,9 @@ typedef union VTDInvDesc VTDInvDesc;
#define VTD_INV_DESC_PIOTLB_PSI_IN_PASID (3ULL << 4)
#define VTD_INV_DESC_PIOTLB_DID(val) (((val) >> 16) & VTD_DOMAIN_ID_MASK)
#define VTD_INV_DESC_PIOTLB_PASID(val) (((val) >> 32) & 0xfffffULL)
+#define VTD_INV_DESC_PIOTLB_AM(val) ((val) & 0x3fULL)
+#define VTD_INV_DESC_PIOTLB_IH(val) (((val) >> 6) & 0x1)
+#define VTD_INV_DESC_PIOTLB_ADDR(val) ((val) & ~0xfffULL)
#define VTD_INV_DESC_PIOTLB_RSVD_VAL0 0xfff000000000f1c0ULL
#define VTD_INV_DESC_PIOTLB_RSVD_VAL1 0xf80ULL
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 0ba94d1d03..2ba5ffbf5b 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -322,6 +322,28 @@ static gboolean vtd_hash_remove_by_page(gpointer key,
gpointer value,
return (entry->gfn & info->mask) == gfn || entry->gfn == gfn_tlb;
}
+static gboolean vtd_hash_remove_by_page_piotlb(gpointer key, gpointer value,
+ gpointer user_data)
+{
+ VTDIOTLBEntry *entry = (VTDIOTLBEntry *)value;
+ VTDIOTLBPageInvInfo *info = (VTDIOTLBPageInvInfo *)user_data;
+ uint64_t gfn = (info->addr >> VTD_PAGE_SHIFT_4K) & info->mask;
+ uint64_t gfn_tlb = (info->addr & entry->mask) >> VTD_PAGE_SHIFT_4K;
+
+ /*
+ * According to spec, PASID-based-IOTLB Invalidation in page granularity
+ * doesn't invalidate IOTLB entries caching second-stage (PGTT=010b)
+ * or pass-through (PGTT=100b) mappings. Nested isn't supported yet,
+ * so only need to check first-stage (PGTT=001b) mappings.
+ */
+ if (entry->pgtt != VTD_SM_PASID_ENTRY_FLT) {
+ return false;
+ }
+
+ return entry->domain_id == info->domain_id && entry->pasid == info->pasid
&&
+ ((entry->gfn & info->mask) == gfn || entry->gfn == gfn_tlb);
+}
+
/* Reset all the gen of VTDAddressSpace to zero and set the gen of
* IntelIOMMUState to 1. Must be called with IOMMU lock held.
*/
@@ -2937,11 +2959,29 @@ static void vtd_piotlb_pasid_invalidate(IntelIOMMUState
*s,
}
}
+static void vtd_piotlb_page_invalidate(IntelIOMMUState *s, uint16_t domain_id,
+ uint32_t pasid, hwaddr addr, uint8_t am)
+{
+ VTDIOTLBPageInvInfo info;
+
+ info.domain_id = domain_id;
+ info.pasid = pasid;
+ info.addr = addr;
+ info.mask = ~((1 << am) - 1);
+
+ vtd_iommu_lock(s);
+ g_hash_table_foreach_remove(s->iotlb,
+ vtd_hash_remove_by_page_piotlb, &info);
+ vtd_iommu_unlock(s);
+}
+
static bool vtd_process_piotlb_desc(IntelIOMMUState *s,
VTDInvDesc *inv_desc)
{
uint16_t domain_id;
uint32_t pasid;
+ hwaddr addr;
+ uint8_t am;
uint64_t mask[4] = {VTD_INV_DESC_PIOTLB_RSVD_VAL0,
VTD_INV_DESC_PIOTLB_RSVD_VAL1,
VTD_INV_DESC_ALL_ONE, VTD_INV_DESC_ALL_ONE};
@@ -2959,6 +2999,9 @@ static bool vtd_process_piotlb_desc(IntelIOMMUState *s,
break;
case VTD_INV_DESC_PIOTLB_PSI_IN_PASID:
+ am = VTD_INV_DESC_PIOTLB_AM(inv_desc->val[1]);
+ addr = (hwaddr) VTD_INV_DESC_PIOTLB_ADDR(inv_desc->val[1]);
+ vtd_piotlb_page_invalidate(s, domain_id, pasid, addr, am);
break;
default:
--
2.34.1
- [PATCH v6 03/20] intel_iommu: Add a placeholder variable for scalable mode stage-1 translation, (continued)
- [PATCH v6 03/20] intel_iommu: Add a placeholder variable for scalable mode stage-1 translation, Zhenzhong Duan, 2024/12/12
- [PATCH v6 04/20] intel_iommu: Flush stage-2 cache in PASID-selective PASID-based iotlb invalidation, Zhenzhong Duan, 2024/12/12
- [PATCH v6 05/20] intel_iommu: Rename slpte to pte, Zhenzhong Duan, 2024/12/12
- [PATCH v6 06/20] intel_iommu: Implement stage-1 translation, Zhenzhong Duan, 2024/12/12
- [PATCH v6 07/20] intel_iommu: Check if the input address is canonical, Zhenzhong Duan, 2024/12/12
- [PATCH v6 09/20] intel_iommu: Set accessed and dirty bits during stage-1 translation, Zhenzhong Duan, 2024/12/12
- [PATCH v6 08/20] intel_iommu: Check stage-1 translation result with interrupt range, Zhenzhong Duan, 2024/12/12
- [PATCH v6 10/20] intel_iommu: Flush stage-1 cache in iotlb invalidation, Zhenzhong Duan, 2024/12/12
- [PATCH v6 12/20] intel_iommu: Add an internal API to find an address space with PASID, Zhenzhong Duan, 2024/12/12
- [PATCH v6 14/20] intel_iommu: piotlb invalidation should notify unmap, Zhenzhong Duan, 2024/12/12
- [PATCH v6 11/20] intel_iommu: Process PASID-based iotlb invalidation,
Zhenzhong Duan <=
- [PATCH v6 13/20] intel_iommu: Add support for PASID-based device IOTLB invalidation, Zhenzhong Duan, 2024/12/12
- [PATCH v6 16/20] intel_iommu: Set default aw_bits to 48 starting from QEMU 9.2, Zhenzhong Duan, 2024/12/12
- [PATCH v6 15/20] tests/acpi: q35: allow DMAR acpi table changes, Zhenzhong Duan, 2024/12/12
- [PATCH v6 17/20] tests/acpi: q35: Update host address width in DMAR, Zhenzhong Duan, 2024/12/12
- [PATCH v6 18/20] intel_iommu: Introduce a property x-flts for stage-1 translation, Zhenzhong Duan, 2024/12/12
- [PATCH v6 19/20] intel_iommu: Introduce a property to control FS1GP cap bit setting, Zhenzhong Duan, 2024/12/12
- [PATCH v6 20/20] tests/qtest: Add intel-iommu test, Zhenzhong Duan, 2024/12/12
- Re: [PATCH v6 00/20] intel_iommu: Enable stage-1 translation for emulated device, CLEMENT MATHIEU--DRIF, 2024/12/12