qemu-devel
[Top][All Lists]
Advanced

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [PATCH 3/8] pci/msix: Implement PBA writes


From: Akihiko Odaki
Subject: Re: [PATCH 3/8] pci/msix: Implement PBA writes
Date: Fri, 13 Dec 2024 14:14:40 +0900
User-agent: Mozilla Thunderbird

On 2024/12/12 17:34, Nicholas Piggin wrote:
Implement MMIO PBA writes, 1 to trigger and 0 to clear.

This functionality is used by some qtests, which keep the msix irq
masked and test irq pending via the PBA bits, for simplicity. Some
tests expect to be able to clear the irq with a store, so a side-effect
of this is that qpci_msix_pending() would actually clear the pending
bit where it previously did not. This actually causes some [possibly
buggy] tests to fail. So to avoid breakage until tests are re-examined,
prior behavior of qpci_msix_pending() is kept by changing it to avoid
clearing PBA.

A new function qpci_msix_test_clear_pending() is added for tests that
do want the PBA clearing, and it will be used by XHCI and e1000e/igb
tests in subsequent changes.

The specification says software should never write Pending Bits and its result is undefined. Tests should have an alternative method to clear Pending Bits.

A possible solution is to unmask the interrupt, wait until the Pending Bits get cleared, and mask it again.



reply via email to

[Prev in Thread] Current Thread [Next in Thread]