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[PULL 32/39] target/riscv: Check memory access to meet svukte rule
From: |
Alistair Francis |
Subject: |
[PULL 32/39] target/riscv: Check memory access to meet svukte rule |
Date: |
Thu, 19 Dec 2024 08:30:02 +1000 |
From: "Fea.Wang" <fea.wang@sifive.com>
Follow the Svukte spec, do the memory access address checking
1. Include instruction fetches or explicit memory accesses
2. System run in effective privilege U or VU
3. Check senvcfg[UKTE] being set, or hstatus[HUKTE] being set if
instruction is HLV, HLVX, HSV and execute from U mode to VU mode
4. Depend on Sv39 and check virtual addresses bit[SXLEN-1]
5. Raises a page-fault exception corresponding to the original access
type.
Ref: https://github.com/riscv/riscv-isa-manual/pull/1564/files
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Fea.Wang <fea.wang@sifive.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241203034932.25185-5-fea.wang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 55 +++++++++++++++++++++++++++++++++++++++
1 file changed, 55 insertions(+)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 45806f5ab0..750c0537ca 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -857,6 +857,55 @@ static int get_physical_address_pmp(CPURISCVState *env,
int *prot, hwaddr addr,
return TRANSLATE_SUCCESS;
}
+/* Returns 'true' if a svukte address check is needed */
+static bool do_svukte_check(CPURISCVState *env, bool first_stage,
+ int mode, bool virt)
+{
+ /* Svukte extension depends on Sv39. */
+ if (!(env_archcpu(env)->cfg.ext_svukte ||
+ !first_stage ||
+ VM_1_10_SV39 != get_field(env->satp, SATP64_MODE))) {
+ return false;
+ }
+
+ /*
+ * Check hstatus.HUKTE if the effective mode is switched to VU-mode by
+ * executing HLV/HLVX/HSV in U-mode.
+ * For other cases, check senvcfg.UKTE.
+ */
+ if (env->priv == PRV_U && !env->virt_enabled && virt) {
+ if (!get_field(env->hstatus, HSTATUS_HUKTE)) {
+ return false;
+ }
+ } else if (!get_field(env->senvcfg, SENVCFG_UKTE)) {
+ return false;
+ }
+
+ /*
+ * Svukte extension is qualified only in U or VU-mode.
+ *
+ * Effective mode can be switched to U or VU-mode by:
+ * - M-mode + mstatus.MPRV=1 + mstatus.MPP=U-mode.
+ * - Execute HLV/HLVX/HSV from HS-mode + hstatus.SPVP=0.
+ * - U-mode.
+ * - VU-mode.
+ * - Execute HLV/HLVX/HSV from U-mode + hstatus.HU=1.
+ */
+ if (mode != PRV_U) {
+ return false;
+ }
+
+ return true;
+}
+
+static bool check_svukte_addr(CPURISCVState *env, vaddr addr)
+{
+ /* svukte extension excludes RV32 */
+ uint32_t sxlen = 32 * riscv_cpu_sxl(env);
+ uint64_t high_bit = addr & (1UL << (sxlen - 1));
+ return !high_bit;
+}
+
/*
* get_physical_address - get the physical address for this virtual address
*
@@ -894,6 +943,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr
*physical,
MemTxResult res;
MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
int mode = mmuidx_priv(mmu_idx);
+ bool virt = mmuidx_2stage(mmu_idx);
bool use_background = false;
hwaddr ppn;
int napot_bits = 0;
@@ -901,6 +951,11 @@ static int get_physical_address(CPURISCVState *env, hwaddr
*physical,
bool is_sstack_idx = ((mmu_idx & MMU_IDX_SS_WRITE) == MMU_IDX_SS_WRITE);
bool sstack_page = false;
+ if (do_svukte_check(env, first_stage, mode, virt) &&
+ !check_svukte_addr(env, addr)) {
+ return TRANSLATE_FAIL;
+ }
+
/*
* Check if we should use the background registers for the two
* stage translation. We don't need to check if we actually need
--
2.47.1
- [PULL 09/39] docs/specs: add riscv-iommu-sys information, (continued)
- [PULL 09/39] docs/specs: add riscv-iommu-sys information, Alistair Francis, 2024/12/18
- [PULL 12/39] hw/riscv/virt.c: reduce virt_use_kvm_aia() usage, Alistair Francis, 2024/12/18
- [PULL 10/39] target/riscv: Add Tenstorrent Ascalon CPU, Alistair Francis, 2024/12/18
- [PULL 08/39] hw/riscv/riscv-iommu: implement reset protocol, Alistair Francis, 2024/12/18
- [PULL 13/39] hw/riscv/virt.c: rename helper to virt_use_kvm_aia_aplic_imsic(), Alistair Francis, 2024/12/18
- [PULL 15/39] hw/riscv/virt.c, riscv_aplic.c: add 'emulated_aplic' helpers, Alistair Francis, 2024/12/18
- [PULL 16/39] hw/intc/riscv_aplic: add kvm_msicfgaddr for split mode aplic-imsic, Alistair Francis, 2024/12/18
- [PULL 14/39] target/riscv/kvm: consider irqchip_split() in aia_create(), Alistair Francis, 2024/12/18
- [PULL 21/39] hw/acpi: Upgrade ACPI SPCR table to support SPCR table revision 4 format, Alistair Francis, 2024/12/18
- [PULL 24/39] hw/char/riscv_htif: Explicit little-endian implementation, Alistair Francis, 2024/12/18
- [PULL 32/39] target/riscv: Check memory access to meet svukte rule,
Alistair Francis <=
- [PULL 19/39] hw/riscv: Add Microblaze V generic board, Alistair Francis, 2024/12/18
- [PULL 22/39] tests/qtest/bios-tables-test: Update virt SPCR golden reference for RISC-V, Alistair Francis, 2024/12/18
- [PULL 26/39] hw/riscv: Support to load DTB after 3GB memory on 64-bit system., Alistair Francis, 2024/12/18
- [PULL 39/39] target/riscv: add support for RV64 Xiangshan Nanhu CPU, Alistair Francis, 2024/12/18
- [PULL 27/39] hw/riscv: Add a new struct RISCVBootInfo, Alistair Francis, 2024/12/18
- [PULL 20/39] qtest: allow SPCR acpi table changes, Alistair Francis, 2024/12/18
- [PULL 28/39] hw/riscv: Add the checking if DTB overlaps to kernel or initrd, Alistair Francis, 2024/12/18
- [PULL 31/39] target/riscv: Support hstatus[HUKTE] bit when svukte extension is enabled, Alistair Francis, 2024/12/18
- [PULL 33/39] target/riscv: Expose svukte ISA extension, Alistair Francis, 2024/12/18
- [PULL 37/39] target/riscv/tcg: hide warn for named feats when disabling via priv_ver, Alistair Francis, 2024/12/18