[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 33/39] target/riscv: Expose svukte ISA extension
|
From: |
Alistair Francis |
|
Subject: |
[PULL 33/39] target/riscv: Expose svukte ISA extension |
|
Date: |
Thu, 19 Dec 2024 08:30:03 +1000 |
From: "Fea.Wang" <fea.wang@sifive.com>
Add "svukte" in the ISA string when svukte extension is enabled.
Signed-off-by: Fea.Wang <fea.wang@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241203034932.25185-6-fea.wang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 66e00ed260..18f4d94b6e 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -199,6 +199,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval),
ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot),
ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt),
+ ISA_EXT_DATA_ENTRY(svukte, PRIV_VERSION_1_13_0, ext_svukte),
ISA_EXT_DATA_ENTRY(svvptc, PRIV_VERSION_1_13_0, ext_svvptc),
ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba),
ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb),
@@ -1663,6 +1664,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
/* These are experimental so mark with 'x-' */
const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
+ MULTI_EXT_CFG_BOOL("x-svukte", ext_svukte, false),
DEFINE_PROP_END_OF_LIST(),
};
--
2.47.1
- [PULL 24/39] hw/char/riscv_htif: Explicit little-endian implementation, (continued)
- [PULL 24/39] hw/char/riscv_htif: Explicit little-endian implementation, Alistair Francis, 2024/12/18
- [PULL 32/39] target/riscv: Check memory access to meet svukte rule, Alistair Francis, 2024/12/18
- [PULL 19/39] hw/riscv: Add Microblaze V generic board, Alistair Francis, 2024/12/18
- [PULL 22/39] tests/qtest/bios-tables-test: Update virt SPCR golden reference for RISC-V, Alistair Francis, 2024/12/18
- [PULL 26/39] hw/riscv: Support to load DTB after 3GB memory on 64-bit system., Alistair Francis, 2024/12/18
- [PULL 39/39] target/riscv: add support for RV64 Xiangshan Nanhu CPU, Alistair Francis, 2024/12/18
- [PULL 27/39] hw/riscv: Add a new struct RISCVBootInfo, Alistair Francis, 2024/12/18
- [PULL 20/39] qtest: allow SPCR acpi table changes, Alistair Francis, 2024/12/18
- [PULL 28/39] hw/riscv: Add the checking if DTB overlaps to kernel or initrd, Alistair Francis, 2024/12/18
- [PULL 31/39] target/riscv: Support hstatus[HUKTE] bit when svukte extension is enabled, Alistair Francis, 2024/12/18
- [PULL 33/39] target/riscv: Expose svukte ISA extension,
Alistair Francis <=
- [PULL 37/39] target/riscv/tcg: hide warn for named feats when disabling via priv_ver, Alistair Francis, 2024/12/18
- [PULL 17/39] target/riscv/kvm: remove irqchip_split() restriction, Alistair Francis, 2024/12/18
- [PULL 25/39] hw/char/riscv_htif: Clarify MemoryRegionOps expect 32-bit accesses, Alistair Francis, 2024/12/18
- [PULL 29/39] target/riscv: Add svukte extension capability variable, Alistair Francis, 2024/12/18
- [PULL 35/39] target/riscv: Include missing headers in 'vector_internals.h', Alistair Francis, 2024/12/18
- [PULL 34/39] target/riscv: Check svukte is not enabled in RV32, Alistair Francis, 2024/12/18
- [PULL 23/39] MAINTAINERS: Cover RISC-V HTIF interface, Alistair Francis, 2024/12/18
- [PULL 30/39] target/riscv: Support senvcfg[UKTE] bit when svukte extension is enabled, Alistair Francis, 2024/12/18
- [PULL 38/39] target/riscv: add ssstateen, Alistair Francis, 2024/12/18
- [PULL 18/39] docs: update riscv/virt.rst with kernel-irqchip=split support, Alistair Francis, 2024/12/18