[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH] hw/mem: support zero memory size CXL device
From: |
Jonathan Cameron |
Subject: |
Re: [PATCH] hw/mem: support zero memory size CXL device |
Date: |
Tue, 24 Dec 2024 15:13:15 +0000 |
On Tue, 10 Dec 2024 14:13:29 -0500
Gregory Price <gourry@gourry.net> wrote:
> On Tue, Dec 03, 2024 at 09:15:51PM +0000, Hongjian Fan wrote:
> > Hi Jonathan,
> >
> > I'm trying to emulate our memory appliance which is similar to a MH-SLD.
> > The memory device is connected to the host server while the size of the
> > memory could be changed by the out-of-band fabric manager. If there is no
> > memory assigned to the host, the CXL device will be booted as zero memory
> > size.
>
> This should not be how this is done.
Agreed, but...
It sounds like a pre DCD boot time only pooling solution?
What is the path to adding memory?
>
> The ACPI tables should report the maximum possible size, and the DCD
> infrastructure should enable physical regions that have been added to the
> host.
>
> Changing ACPI tables to report 0 memory size will basically result
> in the host memory map not reserving physical memory regions for that
> device.
This isn't the ACPI bit, it's just the device reporting. Can have a huge
CFMWS and tiny devices.
>
> See this emulation example of an MHSLD - which can be used for DCD.
>
> https://lore.kernel.org/linux-cxl/20241018161252.8896-1-gourry@gourry.net/
>
> > Recently we got some interest on trying our fabric manager software without
> > having the real hardware. Supporting zero memory size in QEMU will be
> > needed in this scenario.
> > Some detail about our memory appliance could be found from our OCP
> > presentation:
> > https://drive.google.com/file/d/1i8kBsBfRGjNqnTQqJ9upC-Xm9o56Y2Y5/view?usp=drive_link
That doesn't really give me any indication of how the addition of memory
happens.
Jonathan
> >
> > Thanks,
> > Hongjian Fan
> >
> >
> > Seagate Internal