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[Qemu-ppc] [PULL 49/62] ppc/pnv: add SerIRQ routing registers
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 49/62] ppc/pnv: add SerIRQ routing registers |
Date: |
Tue, 12 Mar 2019 19:54:49 +1100 |
From: Cédric Le Goater <address@hidden>
This is just a simple reminder that SerIRQ routing should be
addressed.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
hw/ppc/pnv_lpc.c | 14 ++++++++++++++
include/hw/ppc/pnv_lpc.h | 2 ++
2 files changed, 16 insertions(+)
diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c
index 6df694e0ab..641e2046db 100644
--- a/hw/ppc/pnv_lpc.c
+++ b/hw/ppc/pnv_lpc.c
@@ -39,6 +39,8 @@ enum {
};
/* OPB Master LS registers */
+#define OPB_MASTER_LS_ROUTE0 0x8
+#define OPB_MASTER_LS_ROUTE1 0xC
#define OPB_MASTER_LS_IRQ_STAT 0x50
#define OPB_MASTER_IRQ_LPC 0x00000800
#define OPB_MASTER_LS_IRQ_MASK 0x54
@@ -521,6 +523,12 @@ static uint64_t opb_master_read(void *opaque, hwaddr addr,
unsigned size)
uint64_t val = 0xfffffffffffffffful;
switch (addr) {
+ case OPB_MASTER_LS_ROUTE0: /* TODO */
+ val = lpc->opb_irq_route0;
+ break;
+ case OPB_MASTER_LS_ROUTE1: /* TODO */
+ val = lpc->opb_irq_route1;
+ break;
case OPB_MASTER_LS_IRQ_STAT:
val = lpc->opb_irq_stat;
break;
@@ -547,6 +555,12 @@ static void opb_master_write(void *opaque, hwaddr addr,
PnvLpcController *lpc = opaque;
switch (addr) {
+ case OPB_MASTER_LS_ROUTE0: /* TODO */
+ lpc->opb_irq_route0 = val;
+ break;
+ case OPB_MASTER_LS_ROUTE1: /* TODO */
+ lpc->opb_irq_route1 = val;
+ break;
case OPB_MASTER_LS_IRQ_STAT:
lpc->opb_irq_stat &= ~val;
pnv_lpc_eval_irqs(lpc);
diff --git a/include/hw/ppc/pnv_lpc.h b/include/hw/ppc/pnv_lpc.h
index 242b18081c..413579792e 100644
--- a/include/hw/ppc/pnv_lpc.h
+++ b/include/hw/ppc/pnv_lpc.h
@@ -55,6 +55,8 @@ typedef struct PnvLpcController {
MemoryRegion opb_master_regs;
/* OPB Master LS registers */
+ uint32_t opb_irq_route0;
+ uint32_t opb_irq_route1;
uint32_t opb_irq_stat;
uint32_t opb_irq_mask;
uint32_t opb_irq_pol;
--
2.20.1
- [Qemu-ppc] [PULL 41/62] mac_oldworld: use node name instead of alias name for hd device in FWPathProvider, (continued)
- [Qemu-ppc] [PULL 41/62] mac_oldworld: use node name instead of alias name for hd device in FWPathProvider, David Gibson, 2019/03/12
- [Qemu-ppc] [PULL 44/62] ppc/pnv: add a PSI bridge model for POWER9, David Gibson, 2019/03/12
- [Qemu-ppc] [PULL 33/62] spapr_iommu: Do not replay mappings from just created DMA window, David Gibson, 2019/03/12
- [Qemu-ppc] [PULL 43/62] ppc/pnv: add a PSI bridge class model, David Gibson, 2019/03/12
- [Qemu-ppc] [PULL 36/62] target/ppc: move Vsr* macros from internal.h to cpu.h, David Gibson, 2019/03/12
- [Qemu-ppc] [PULL 39/62] target/ppc: switch fpr/vsrl registers so all VSX registers are in host endian order, David Gibson, 2019/03/12
- [Qemu-ppc] [PULL 42/62] mac_newworld: use node name instead of alias name for hd device in FWPathProvider, David Gibson, 2019/03/12
- [Qemu-ppc] [PULL 47/62] ppc/pnv: add a 'dt_isa_nodename' to the chip, David Gibson, 2019/03/12
- [Qemu-ppc] [PULL 38/62] target/ppc: improve avr64_offset() and use it to simplify get_avr64()/set_avr64(), David Gibson, 2019/03/12
- [Qemu-ppc] [PULL 46/62] ppc/pnv: add a LPC Controller class model, David Gibson, 2019/03/12
- [Qemu-ppc] [PULL 49/62] ppc/pnv: add SerIRQ routing registers,
David Gibson <=
- [Qemu-ppc] [PULL 51/62] ppc/pnv: add a OCC model for POWER9, David Gibson, 2019/03/12
- [Qemu-ppc] [PULL 53/62] ppc/pnv: POWER9 XSCOM quad support, David Gibson, 2019/03/12
- [Qemu-ppc] [PULL 45/62] ppc/pnv: lpc: fix OPB address ranges, David Gibson, 2019/03/12
- [Qemu-ppc] [PULL 58/62] target/ppc: Optimize xviexpdp() using deposit_i64(), David Gibson, 2019/03/12
- [Qemu-ppc] [PULL 55/62] ppc/pnv: add more dummy XSCOM addresses, David Gibson, 2019/03/12
- [Qemu-ppc] [PULL 62/62] vfio: Make vfio_get_region_info_cap public, David Gibson, 2019/03/12
- [Qemu-ppc] [PULL 59/62] target/ppc: Optimize x[sv]xsigdp using deposit_i64(), David Gibson, 2019/03/12
- [Qemu-ppc] [PULL 57/62] target/ppc: add HV support for POWER9, David Gibson, 2019/03/12
- [Qemu-ppc] [PULL 54/62] ppc/pnv: activate XSCOM tests for POWER9, David Gibson, 2019/03/12
- [Qemu-ppc] [PULL 56/62] ppc/pnv: add a "ibm, opal/power-mgt" device tree node on POWER9, David Gibson, 2019/03/12