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[Qemu-ppc] [PULL 58/62] target/ppc: Optimize xviexpdp() using deposit_i6
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 58/62] target/ppc: Optimize xviexpdp() using deposit_i64() |
Date: |
Tue, 12 Mar 2019 19:54:58 +1100 |
From: Philippe Mathieu-Daudé <address@hidden>
The t0 tcg_temp register is now unused, remove it.
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/translate/vsx-impl.inc.c | 14 +++-----------
1 file changed, 3 insertions(+), 11 deletions(-)
diff --git a/target/ppc/translate/vsx-impl.inc.c
b/target/ppc/translate/vsx-impl.inc.c
index 95a269fff0..30d8aabd92 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -1695,7 +1695,6 @@ static void gen_xviexpdp(DisasContext *ctx)
TCGv_i64 xal;
TCGv_i64 xbh;
TCGv_i64 xbl;
- TCGv_i64 t0;
if (unlikely(!ctx->vsx_enabled)) {
gen_exception(ctx, POWERPC_EXCP_VSXU);
@@ -1711,20 +1710,13 @@ static void gen_xviexpdp(DisasContext *ctx)
get_cpu_vsrl(xal, xA(ctx->opcode));
get_cpu_vsrh(xbh, xB(ctx->opcode));
get_cpu_vsrl(xbl, xB(ctx->opcode));
- t0 = tcg_temp_new_i64();
- tcg_gen_andi_i64(xth, xah, 0x800FFFFFFFFFFFFF);
- tcg_gen_andi_i64(t0, xbh, 0x7FF);
- tcg_gen_shli_i64(t0, t0, 52);
- tcg_gen_or_i64(xth, xth, t0);
+ tcg_gen_deposit_i64(xth, xah, xbh, 52, 11);
set_cpu_vsrh(xT(ctx->opcode), xth);
- tcg_gen_andi_i64(xtl, xal, 0x800FFFFFFFFFFFFF);
- tcg_gen_andi_i64(t0, xbl, 0x7FF);
- tcg_gen_shli_i64(t0, t0, 52);
- tcg_gen_or_i64(xtl, xtl, t0);
+
+ tcg_gen_deposit_i64(xtl, xal, xbl, 52, 11);
set_cpu_vsrl(xT(ctx->opcode), xtl);
- tcg_temp_free_i64(t0);
tcg_temp_free_i64(xth);
tcg_temp_free_i64(xtl);
tcg_temp_free_i64(xah);
--
2.20.1
- [Qemu-ppc] [PULL 36/62] target/ppc: move Vsr* macros from internal.h to cpu.h, (continued)
- [Qemu-ppc] [PULL 36/62] target/ppc: move Vsr* macros from internal.h to cpu.h, David Gibson, 2019/03/12
- [Qemu-ppc] [PULL 39/62] target/ppc: switch fpr/vsrl registers so all VSX registers are in host endian order, David Gibson, 2019/03/12
- [Qemu-ppc] [PULL 42/62] mac_newworld: use node name instead of alias name for hd device in FWPathProvider, David Gibson, 2019/03/12
- [Qemu-ppc] [PULL 47/62] ppc/pnv: add a 'dt_isa_nodename' to the chip, David Gibson, 2019/03/12
- [Qemu-ppc] [PULL 38/62] target/ppc: improve avr64_offset() and use it to simplify get_avr64()/set_avr64(), David Gibson, 2019/03/12
- [Qemu-ppc] [PULL 46/62] ppc/pnv: add a LPC Controller class model, David Gibson, 2019/03/12
- [Qemu-ppc] [PULL 49/62] ppc/pnv: add SerIRQ routing registers, David Gibson, 2019/03/12
- [Qemu-ppc] [PULL 51/62] ppc/pnv: add a OCC model for POWER9, David Gibson, 2019/03/12
- [Qemu-ppc] [PULL 53/62] ppc/pnv: POWER9 XSCOM quad support, David Gibson, 2019/03/12
- [Qemu-ppc] [PULL 45/62] ppc/pnv: lpc: fix OPB address ranges, David Gibson, 2019/03/12
- [Qemu-ppc] [PULL 58/62] target/ppc: Optimize xviexpdp() using deposit_i64(),
David Gibson <=
- [Qemu-ppc] [PULL 55/62] ppc/pnv: add more dummy XSCOM addresses, David Gibson, 2019/03/12
- [Qemu-ppc] [PULL 62/62] vfio: Make vfio_get_region_info_cap public, David Gibson, 2019/03/12
- [Qemu-ppc] [PULL 59/62] target/ppc: Optimize x[sv]xsigdp using deposit_i64(), David Gibson, 2019/03/12
- [Qemu-ppc] [PULL 57/62] target/ppc: add HV support for POWER9, David Gibson, 2019/03/12
- [Qemu-ppc] [PULL 54/62] ppc/pnv: activate XSCOM tests for POWER9, David Gibson, 2019/03/12
- [Qemu-ppc] [PULL 56/62] ppc/pnv: add a "ibm, opal/power-mgt" device tree node on POWER9, David Gibson, 2019/03/12
- [Qemu-ppc] [PULL 50/62] ppc/pnv: add a OCC model class, David Gibson, 2019/03/12
- [Qemu-ppc] [PULL 61/62] Suppress test warnings about missing Spectre/Meltdown mitigations with TCG, David Gibson, 2019/03/12
- [Qemu-ppc] [PULL 48/62] ppc/pnv: add a LPC Controller model for POWER9, David Gibson, 2019/03/12
- [Qemu-ppc] [PULL 52/62] ppc/pnv: extend XSCOM core support for POWER9, David Gibson, 2019/03/12