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[PULL 01/15] ppc/pnv: Fix NMI system reset SRR1 value
From: |
David Gibson |
Subject: |
[PULL 01/15] ppc/pnv: Fix NMI system reset SRR1 value |
Date: |
Wed, 27 May 2020 15:37:55 +1000 |
From: Nicholas Piggin <address@hidden>
Commit a77fed5bd926 ("ppc/pnv: Add support for NMI interface") got the
SRR1 setting wrong for sresets that hit outside of power-save states.
Fix this, better documenting the source for the bit definitions.
Fixes: 01b552b05b0f ("ppc/pnv: Add support for NMI interface")
Cc: Cédric Le Goater <address@hidden>
Cc: David Gibson <address@hidden>
Signed-off-by: Nicholas Piggin <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
[dwg: Fixed up some tab indentation]
Signed-off-by: David Gibson <address@hidden>
---
hw/ppc/pnv.c | 26 ++++++++++++++++++++------
1 file changed, 20 insertions(+), 6 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index da637822f9..f48a61d6d1 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1984,12 +1984,26 @@ static void pnv_cpu_do_nmi_on_cpu(CPUState *cs,
run_on_cpu_data arg)
cpu_synchronize_state(cs);
ppc_cpu_do_system_reset(cs);
- /*
- * SRR1[42:45] is set to 0100 which the ISA defines as implementation
- * dependent. POWER processors use this for xscom triggered interrupts,
- * which come from the BMC or NMI IPIs.
- */
- env->spr[SPR_SRR1] |= PPC_BIT(43);
+ if (env->spr[SPR_SRR1] & PPC_BITMASK(46, 47)) {
+ /*
+ * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the
+ * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100
+ * (PPC_BIT(43)).
+ */
+ if (!(env->spr[SPR_SRR1] & PPC_BIT(43))) {
+ warn_report("ppc_cpu_do_system_reset does not set system reset
wakeup reason");
+ env->spr[SPR_SRR1] |= PPC_BIT(43);
+ }
+ } else {
+ /*
+ * For non-powersave system resets, SRR1[42:45] are defined to be
+ * implementation-dependent. The POWER9 User Manual specifies that
+ * an external (SCOM driven, which may come from a BMC nmi command or
+ * another CPU requesting a NMI IPI) system reset exception should be
+ * 0b0010 (PPC_BIT(44)).
+ */
+ env->spr[SPR_SRR1] |= PPC_BIT(44);
+ }
}
static void pnv_nmi(NMIState *n, int cpu_index, Error **errp)
--
2.26.2
- [PULL 00/15] ppc-for-5.1 queue 20200527, David Gibson, 2020/05/27
- [PULL 03/15] target/ppc: Untabify excp_helper.c, David Gibson, 2020/05/27
- [PULL 01/15] ppc/pnv: Fix NMI system reset SRR1 value,
David Gibson <=
- [PULL 08/15] target/ppc: Don't initialize some local variables in ppc_radix64_xlate(), David Gibson, 2020/05/27
- [PULL 05/15] ppc/spapr: Add hotremovable flag on DIMM LMBs on drmem_v2, David Gibson, 2020/05/27
- [PULL 02/15] ppc/spapr: add a POWER10 CPU model, David Gibson, 2020/05/27
- [PULL 10/15] target/ppc: Fix arguments to ppc_radix64_partition_scoped_xlate(), David Gibson, 2020/05/27
- [PULL 07/15] target/ppc: Pass const pointer to ppc_radix64_get_fully_qualified_addr(), David Gibson, 2020/05/27
- [PULL 06/15] target/ppc: Pass const pointer to ppc_radix64_get_prot_amr(), David Gibson, 2020/05/27
- [PULL 12/15] hw/pci-bridge/dec: Remove dead debug code, David Gibson, 2020/05/27
- [PULL 04/15] target/ppc: Add support for scv and rfscv instructions, David Gibson, 2020/05/27
- [PULL 09/15] target/ppc: Add missing braces in ppc_radix64_partition_scoped_xlate(), David Gibson, 2020/05/27
- [PULL 11/15] target/ppc: Don't update radix PTE R/C bits with gdbstub, David Gibson, 2020/05/27