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[PATCH v3 17/21] target/ppc: Remove msr_fe0 and msr_fe1 macros
From: |
Víctor Colombo |
Subject: |
[PATCH v3 17/21] target/ppc: Remove msr_fe0 and msr_fe1 macros |
Date: |
Tue, 3 May 2022 17:24:37 -0300 |
msr_fe0 and msr_fe1 macros hide the usage of env->msr, which is a bad
behavior. Substitute it with FIELD_EX64 calls that explicitly use
env->msr as a parameter.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
---
v3: Added a combined macro for FE0 and FE1. Use it to simplify
conditionals. Removed Richard's R-b because of this change.
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
---
target/ppc/cpu.h | 11 +++++++++--
target/ppc/excp_helper.c | 18 ++++++------------
2 files changed, 15 insertions(+), 14 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 9683e6a359..cc7ca1d47d 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -363,12 +363,21 @@ FIELD(MSR, EE, MSR_EE, 1)
FIELD(MSR, PR, MSR_PR, 1)
FIELD(MSR, FP, MSR_FP, 1)
FIELD(MSR, ME, MSR_ME, 1)
+FIELD(MSR, FE0, MSR_FE0, 1)
+FIELD(MSR, FE1, MSR_FE1, 1)
FIELD(MSR, EP, MSR_EP, 1)
FIELD(MSR, IR, MSR_IR, 1)
FIELD(MSR, DR, MSR_DR, 1)
FIELD(MSR, DS, MSR_DS, 1)
FIELD(MSR, LE, MSR_LE, 1)
+/*
+ * FE0 and FE1 bits are not side-by-side
+ * so we can't combine them using FIELD()
+ */
+#define FIELD_EX64_FE(msr) \
+ ((FIELD_EX64(msr, MSR, FE0) << 1) | FIELD_EX64(msr, MSR, FE1))
+
/* PMU bits */
#define MMCR0_FC PPC_BIT(32) /* Freeze Counters */
#define MMCR0_PMAO PPC_BIT(56) /* Perf Monitor Alert Ocurred */
@@ -484,8 +493,6 @@ FIELD(MSR, LE, MSR_LE, 1)
#else
#define msr_hv (0)
#endif
-#define msr_fe0 ((env->msr >> MSR_FE0) & 1)
-#define msr_fe1 ((env->msr >> MSR_FE1) & 1)
#define msr_ts ((env->msr >> MSR_TS1) & 3)
#define DBCR0_ICMP (1 << 27)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 30baad0489..aa201c63c6 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -478,8 +478,7 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_PROGRAM: /* Program exception */
switch (env->error_code & ~0xF) {
case POWERPC_EXCP_FP:
- if ((msr_fe0 == 0 && msr_fe1 == 0) ||
- !FIELD_EX64(env->msr, MSR, FP)) {
+ if (!FIELD_EX64_FE(env->msr) || !FIELD_EX64(env->msr, MSR, FP)) {
trace_ppc_excp_fp_ignore();
powerpc_reset_excp_state(cpu);
return;
@@ -616,8 +615,7 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_PROGRAM: /* Program exception */
switch (env->error_code & ~0xF) {
case POWERPC_EXCP_FP:
- if ((msr_fe0 == 0 && msr_fe1 == 0) ||
- !FIELD_EX64(env->msr, MSR, FP)) {
+ if (!FIELD_EX64_FE(env->msr) || !FIELD_EX64(env->msr, MSR, FP)) {
trace_ppc_excp_fp_ignore();
powerpc_reset_excp_state(cpu);
return;
@@ -790,8 +788,7 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_PROGRAM: /* Program exception */
switch (env->error_code & ~0xF) {
case POWERPC_EXCP_FP:
- if ((msr_fe0 == 0 && msr_fe1 == 0) ||
- !FIELD_EX64(env->msr, MSR, FP)) {
+ if (!FIELD_EX64_FE(env->msr) || !FIELD_EX64(env->msr, MSR, FP)) {
trace_ppc_excp_fp_ignore();
powerpc_reset_excp_state(cpu);
return;
@@ -976,8 +973,7 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_PROGRAM: /* Program exception */
switch (env->error_code & ~0xF) {
case POWERPC_EXCP_FP:
- if ((msr_fe0 == 0 && msr_fe1 == 0) ||
- !FIELD_EX64(env->msr, MSR, FP)) {
+ if (!FIELD_EX64_FE(env->msr) || !FIELD_EX64(env->msr, MSR, FP)) {
trace_ppc_excp_fp_ignore();
powerpc_reset_excp_state(cpu);
return;
@@ -1175,8 +1171,7 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_PROGRAM: /* Program exception */
switch (env->error_code & ~0xF) {
case POWERPC_EXCP_FP:
- if ((msr_fe0 == 0 && msr_fe1 == 0) ||
- !FIELD_EX64(env->msr, MSR, FP)) {
+ if (!FIELD_EX64_FE(env->msr) || !FIELD_EX64(env->msr, MSR, FP)) {
trace_ppc_excp_fp_ignore();
powerpc_reset_excp_state(cpu);
return;
@@ -1439,8 +1434,7 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_PROGRAM: /* Program exception */
switch (env->error_code & ~0xF) {
case POWERPC_EXCP_FP:
- if ((msr_fe0 == 0 && msr_fe1 == 0) ||
- !FIELD_EX64(env->msr, MSR, FP)) {
+ if (!FIELD_EX64_FE(env->msr) || !FIELD_EX64(env->msr, MSR, FP)) {
trace_ppc_excp_fp_ignore();
powerpc_reset_excp_state(cpu);
return;
--
2.25.1
- [PATCH v3 13/21] target/ppc: Remove msr_cm macro, (continued)
- [PATCH v3 13/21] target/ppc: Remove msr_cm macro, Víctor Colombo, 2022/05/03
- [PATCH v3 11/21] target/ppc: Remove msr_gs macro, Víctor Colombo, 2022/05/03
- [PATCH v3 12/21] target/ppc: Remove msr_fp macro, Víctor Colombo, 2022/05/03
- [PATCH v3 15/21] target/ppc: Remove msr_dr macro, Víctor Colombo, 2022/05/03
- [PATCH v3 14/21] target/ppc: Remove msr_ir macro, Víctor Colombo, 2022/05/03
- [PATCH v3 16/21] target/ppc: Remove msr_ep macro, Víctor Colombo, 2022/05/03
- [PATCH v3 17/21] target/ppc: Remove msr_fe0 and msr_fe1 macros,
Víctor Colombo <=
- [PATCH v3 18/21] target/ppc: Remove msr_ts macro, Víctor Colombo, 2022/05/03
- [PATCH v3 19/21] target/ppc: Remove msr_hv macro, Víctor Colombo, 2022/05/03
- [PATCH v3 20/21] target/ppc: Add unused msr bits FIELDs, Víctor Colombo, 2022/05/03
- [PATCH v3 21/21] target/ppc: Change MSR_* to follow POWER ISA numbering convention, Víctor Colombo, 2022/05/03
- Re: [PATCH v3 00/21] target/ppc: Remove hidden usages of *env, Daniel Henrique Barboza, 2022/05/04