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[PATCH 2/9] target/cris: Use tcg_gen_extract_tl
From: |
Philippe Mathieu-Daudé |
Subject: |
[PATCH 2/9] target/cris: Use tcg_gen_extract_tl |
Date: |
Mon, 23 Oct 2023 18:09:37 +0200 |
Inspired-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/cris/translate.c | 3 +--
target/i386/tcg/translate.c | 9 +++------
2 files changed, 4 insertions(+), 8 deletions(-)
diff --git a/target/cris/translate.c b/target/cris/translate.c
index b3974ba0bb..65b07e1d80 100644
--- a/target/cris/translate.c
+++ b/target/cris/translate.c
@@ -871,8 +871,7 @@ static void gen_tst_cc (DisasContext *dc, TCGv cc, int cond)
bits = 15;
}
- tcg_gen_shri_tl(cc, cc_result, bits);
- tcg_gen_andi_tl(cc, cc, 1);
+ tcg_gen_extract_tl(cc, cc_result, bits, 1);
} else {
cris_evaluate_flags(dc);
tcg_gen_andi_tl(cc, cpu_PR[PR_CCS],
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 587d88692a..25289eeec9 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -1159,8 +1159,7 @@ static void gen_setcc1(DisasContext *s, int b, TCGv reg)
if (cc.cond == TCG_COND_NE && !cc.use_reg2 && cc.imm == 0 &&
cc.mask != 0 && (cc.mask & (cc.mask - 1)) == 0) {
- tcg_gen_shri_tl(reg, cc.reg, ctztl(cc.mask));
- tcg_gen_andi_tl(reg, reg, 1);
+ tcg_gen_extract_tl(reg, cc.reg, ctztl(cc.mask), 1);
return;
}
if (cc.mask != -1) {
@@ -1783,8 +1782,7 @@ static void gen_rot_rm_T1(DisasContext *s, MemOp ot, int
op1, int is_right)
currently dead. */
if (is_right) {
tcg_gen_shri_tl(cpu_cc_src2, s->T0, mask - 1);
- tcg_gen_shri_tl(cpu_cc_dst, s->T0, mask);
- tcg_gen_andi_tl(cpu_cc_dst, cpu_cc_dst, 1);
+ tcg_gen_extract_tl(cpu_cc_dst, s->T0, mask, 1);
} else {
tcg_gen_shri_tl(cpu_cc_src2, s->T0, mask);
tcg_gen_andi_tl(cpu_cc_dst, s->T0, 1);
@@ -1873,8 +1871,7 @@ static void gen_rot_rm_im(DisasContext *s, MemOp ot, int
op1, int op2,
currently dead. */
if (is_right) {
tcg_gen_shri_tl(cpu_cc_src2, s->T0, mask - 1);
- tcg_gen_shri_tl(cpu_cc_dst, s->T0, mask);
- tcg_gen_andi_tl(cpu_cc_dst, cpu_cc_dst, 1);
+ tcg_gen_extract_tl(cpu_cc_dst, s->T0, mask, 1);
} else {
tcg_gen_shri_tl(cpu_cc_src2, s->T0, mask);
tcg_gen_andi_tl(cpu_cc_dst, s->T0, 1);
--
2.41.0
- [PATCH 0/9] tcg: Use tcg_gen_[s]extract_{i32,i64,tl}, Philippe Mathieu-Daudé, 2023/10/23
- [PATCH 1/9] target/avr: Use tcg_gen_extract_tl, Philippe Mathieu-Daudé, 2023/10/23
- [PATCH 2/9] target/cris: Use tcg_gen_extract_tl,
Philippe Mathieu-Daudé <=
- [PATCH 3/9] target/mips: Use tcg_gen_extract_i32, Philippe Mathieu-Daudé, 2023/10/23
- [PATCH 4/9] target/ppc: Use tcg_gen_extract_i32, Philippe Mathieu-Daudé, 2023/10/23
- [PATCH 5/9] target/sparc: Use tcg_gen_extract_tl, Philippe Mathieu-Daudé, 2023/10/23
- [PATCH 6/9] target/xtensa: Use tcg_gen_extract_i32, Philippe Mathieu-Daudé, 2023/10/23