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[PATCH 15/20] target: Implement CPUClass::datapath_is_big_endian (big-en
From: |
Philippe Mathieu-Daudé |
Subject: |
[PATCH 15/20] target: Implement CPUClass::datapath_is_big_endian (big-endian) |
Date: |
Wed, 4 Dec 2024 21:25:57 +0100 |
For all targets which have endianness architecturally
predefined as big endian (built using TARGET_BIG_ENDIAN=y),
their datapath_is_big_endian() handler simply returns %true.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/hexagon/cpu.c | 6 ++++++
target/hppa/cpu.c | 6 ++++++
target/m68k/cpu.c | 6 ++++++
target/openrisc/cpu.c | 6 ++++++
target/s390x/cpu.c | 6 ++++++
5 files changed, 30 insertions(+)
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index 020038fc490..6407ed80c59 100644
--- a/target/hexagon/cpu.c
+++ b/target/hexagon/cpu.c
@@ -245,6 +245,11 @@ void hexagon_debug(CPUHexagonState *env)
hexagon_dump(env, stdout, CPU_DUMP_FPU);
}
+static bool hexagon_cpu_datapath_is_big_endian(CPUState *cs)
+{
+ return true;
+}
+
static void hexagon_cpu_set_pc(CPUState *cs, vaddr value)
{
cpu_env(cs)->gpr[HEX_REG_PC] = value;
@@ -342,6 +347,7 @@ static void hexagon_cpu_class_init(ObjectClass *c, void
*data)
&mcc->parent_phases);
cc->class_by_name = hexagon_cpu_class_by_name;
+ cc->datapath_is_big_endian = hexagon_cpu_datapath_is_big_endian;
cc->has_work = hexagon_cpu_has_work;
cc->dump_state = hexagon_dump_state;
cc->set_pc = hexagon_cpu_set_pc;
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index c38439c1800..8ccd224f2a4 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -203,6 +203,11 @@ static void hppa_cpu_initfn(Object *obj)
cpu_hppa_put_psw(env, PSW_W);
}
+static bool hppa_cpu_datapath_is_big_endian(CPUState *cs)
+{
+ return true;
+}
+
static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model)
{
g_autofree char *typename = g_strconcat(cpu_model, "-cpu", NULL);
@@ -245,6 +250,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data)
&acc->parent_realize);
cc->class_by_name = hppa_cpu_class_by_name;
+ cc->datapath_is_big_endian = hppa_cpu_datapath_is_big_endian;
cc->has_work = hppa_cpu_has_work;
cc->mmu_index = hppa_cpu_mmu_index;
cc->dump_state = hppa_cpu_dump_state;
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index 5fe335558aa..52f8db41d5a 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -24,6 +24,11 @@
#include "migration/vmstate.h"
#include "fpu/softfloat.h"
+static bool m68k_cpu_datapath_is_big_endian(CPUState *cs)
+{
+ return true;
+}
+
static void m68k_cpu_set_pc(CPUState *cs, vaddr value)
{
M68kCPU *cpu = M68K_CPU(cs);
@@ -571,6 +576,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
&mcc->parent_phases);
cc->class_by_name = m68k_cpu_class_by_name;
+ cc->datapath_is_big_endian = m68k_cpu_datapath_is_big_endian;
cc->has_work = m68k_cpu_has_work;
cc->mmu_index = m68k_cpu_mmu_index;
cc->dump_state = m68k_cpu_dump_state;
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index b96561d1f26..16e39b43ec4 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -25,6 +25,11 @@
#include "fpu/softfloat-helpers.h"
#include "tcg/tcg.h"
+static bool openrisc_cpu_datapath_is_big_endian(CPUState *cs)
+{
+ return true;
+}
+
static void openrisc_cpu_set_pc(CPUState *cs, vaddr value)
{
OpenRISCCPU *cpu = OPENRISC_CPU(cs);
@@ -257,6 +262,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void
*data)
&occ->parent_phases);
cc->class_by_name = openrisc_cpu_class_by_name;
+ cc->datapath_is_big_endian = openrisc_cpu_datapath_is_big_endian;
cc->has_work = openrisc_cpu_has_work;
cc->mmu_index = openrisc_cpu_mmu_index;
cc->dump_state = openrisc_cpu_dump_state;
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index 514c70f3010..eda1e3b286f 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -44,6 +44,11 @@
#define CR0_RESET 0xE0UL
#define CR14_RESET 0xC2000000UL;
+static bool s390_cpu_datapath_is_big_endian(CPUState *cs)
+{
+ return true;
+}
+
#ifndef CONFIG_USER_ONLY
static bool is_early_exception_psw(uint64_t mask, uint64_t addr)
{
@@ -390,6 +395,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
&scc->parent_phases);
cc->class_by_name = s390_cpu_class_by_name,
+ cc->datapath_is_big_endian = s390_cpu_datapath_is_big_endian;
cc->has_work = s390_cpu_has_work;
cc->mmu_index = s390x_cpu_mmu_index;
cc->dump_state = s390_cpu_dump_state;
--
2.45.2
- [PATCH 05/20] target/rx: Implement CPUClass::datapath_is_big_endian, (continued)
- [PATCH 05/20] target/rx: Implement CPUClass::datapath_is_big_endian, Philippe Mathieu-Daudé, 2024/12/04
- [PATCH 06/20] target/sparc: Implement CPUClass::datapath_is_big_endian, Philippe Mathieu-Daudé, 2024/12/04
- [PATCH 07/20] target/riscv: Implement CPUClass::datapath_is_big_endian, Philippe Mathieu-Daudé, 2024/12/04
- [PATCH 08/20] target/sh4: Expose CPUSH4State::little_endian property, Philippe Mathieu-Daudé, 2024/12/04
- [PATCH 10/20] target/microblaze: Implement CPUClass::datapath_is_big_endian, Philippe Mathieu-Daudé, 2024/12/04
- [PATCH 09/20] target/sh4: Implement CPUClass::datapath_is_big_endian, Philippe Mathieu-Daudé, 2024/12/04
- [PATCH 11/20] target/mips: Implement CPUClass::datapath_is_big_endian, Philippe Mathieu-Daudé, 2024/12/04
- [PATCH 12/20] target/xtensa: Implement xtensa_isa_is_big_endian(), Philippe Mathieu-Daudé, 2024/12/04
- [PATCH 13/20] target/xtensa: Implement CPUClass::datapath_is_big_endian, Philippe Mathieu-Daudé, 2024/12/04
- [PATCH 14/20] target: Implement CPUClass::datapath_is_big_endian (little-endian), Philippe Mathieu-Daudé, 2024/12/04
- [PATCH 15/20] target: Implement CPUClass::datapath_is_big_endian (big-endian),
Philippe Mathieu-Daudé <=
- [PATCH 16/20] hw/core/cpu: Expose cpu_datapath_is_big_endian() method, Philippe Mathieu-Daudé, 2024/12/04
- [PATCH 17/20] disas: Use cpu_datapath_is_big_endian(), Philippe Mathieu-Daudé, 2024/12/04
- [PATCH 18/20] hw/core/generic-loader: Use cpu_datapath_is_big_endian(), Philippe Mathieu-Daudé, 2024/12/04
- [RFC PATCH 19/20] hw/virtio: Use cpu_datapath_is_big_endian(), Philippe Mathieu-Daudé, 2024/12/04
- [PATCH 20/20] hw/core/cpu: Remove cpu_virtio_is_big_endian(), Philippe Mathieu-Daudé, 2024/12/04