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[PATCH 07/20] target/riscv: Implement CPUClass::datapath_is_big_endian
From: |
Philippe Mathieu-Daudé |
Subject: |
[PATCH 07/20] target/riscv: Implement CPUClass::datapath_is_big_endian |
Date: |
Wed, 4 Dec 2024 21:25:49 +0100 |
While the RISC-V data endianness can be changed at runtime,
we do not implement that. The current translation code assumes
little-endian memory accesses (See commit a2f827ff4f4 "target/riscv:
accessors to registers upper part and 128-bit load/store").
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/riscv/cpu.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f219f0c3b52..b31b9b3471d 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -60,6 +60,22 @@ bool riscv_cpu_is_32bit(RISCVCPU *cpu)
return riscv_cpu_mxl(&cpu->env) == MXL_RV32;
}
+static bool riscv_cpu_datapath_is_big_endian(CPUState *cs)
+{
+#ifndef CONFIG_USER_ONLY
+ /*
+ * A couple of bits in MSTATUS set the endianness:
+ * - MSTATUS_UBE (User-mode),
+ * - MSTATUS_SBE (Supervisor-mode),
+ * - MSTATUS_MBE (Machine-mode)
+ * but we don't implement that yet.
+ */
+ return false;
+#else
+ return false;
+#endif
+}
+
/* Hash that stores general user set numeric options */
static GHashTable *general_user_opts;
@@ -2764,6 +2780,7 @@ static void riscv_cpu_common_class_init(ObjectClass *c,
void *data)
&mcc->parent_phases);
cc->class_by_name = riscv_cpu_class_by_name;
+ cc->datapath_is_big_endian = riscv_cpu_datapath_is_big_endian;
cc->has_work = riscv_cpu_has_work;
cc->mmu_index = riscv_cpu_mmu_index;
cc->dump_state = riscv_cpu_dump_state;
--
2.45.2
- [PATCH 00/20] target: Implement CPUClass::datapath_is_big_endian() handlers, Philippe Mathieu-Daudé, 2024/12/04
- [PATCH 01/20] exec/tswap: Rename target_words_bigendian -> qemu_binary_is_bigendian, Philippe Mathieu-Daudé, 2024/12/04
- [PATCH 02/20] hw/core/cpu: Introduce CPUClass::datapath_is_big_endian() handler, Philippe Mathieu-Daudé, 2024/12/04
- [PATCH 03/20] target/arm: Implement CPUClass::datapath_is_big_endian, Philippe Mathieu-Daudé, 2024/12/04
- [PATCH 04/20] target/ppc: Register CPUClass::datapath_is_big_endian, Philippe Mathieu-Daudé, 2024/12/04
- [PATCH 05/20] target/rx: Implement CPUClass::datapath_is_big_endian, Philippe Mathieu-Daudé, 2024/12/04
- [PATCH 06/20] target/sparc: Implement CPUClass::datapath_is_big_endian, Philippe Mathieu-Daudé, 2024/12/04
- [PATCH 07/20] target/riscv: Implement CPUClass::datapath_is_big_endian,
Philippe Mathieu-Daudé <=
- [PATCH 08/20] target/sh4: Expose CPUSH4State::little_endian property, Philippe Mathieu-Daudé, 2024/12/04
- [PATCH 10/20] target/microblaze: Implement CPUClass::datapath_is_big_endian, Philippe Mathieu-Daudé, 2024/12/04
- [PATCH 09/20] target/sh4: Implement CPUClass::datapath_is_big_endian, Philippe Mathieu-Daudé, 2024/12/04
- [PATCH 11/20] target/mips: Implement CPUClass::datapath_is_big_endian, Philippe Mathieu-Daudé, 2024/12/04
- [PATCH 12/20] target/xtensa: Implement xtensa_isa_is_big_endian(), Philippe Mathieu-Daudé, 2024/12/04
- [PATCH 13/20] target/xtensa: Implement CPUClass::datapath_is_big_endian, Philippe Mathieu-Daudé, 2024/12/04
- [PATCH 14/20] target: Implement CPUClass::datapath_is_big_endian (little-endian), Philippe Mathieu-Daudé, 2024/12/04
- [PATCH 15/20] target: Implement CPUClass::datapath_is_big_endian (big-endian), Philippe Mathieu-Daudé, 2024/12/04
- [PATCH 16/20] hw/core/cpu: Expose cpu_datapath_is_big_endian() method, Philippe Mathieu-Daudé, 2024/12/04