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qemu-riscv (date)
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Last Modified: Thu Nov 29 2018 12:19:45 -0500
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November 29, 2018
Re: [Qemu-riscv] [Qemu-devel] [RFC v2 00/24] Add RISC-V TCG backend support
,
no-reply
,
12:19
November 28, 2018
Re: [Qemu-riscv] [RFC v2 14/24] riscv: tcg-target: Add branch and jump instructions
,
Richard Henderson
,
22:22
Re: [Qemu-riscv] [RFC v2 14/24] riscv: tcg-target: Add branch and jump instructions
,
Alistair Francis
,
20:07
Re: [Qemu-riscv] [RFC v2 19/24] riscv: tcg-target: Add the target init code
,
Richard Henderson
,
15:48
Re: [Qemu-riscv] [RFC v2 18/24] riscv: tcg-target: Add the prologue generation and register the JIT
,
Richard Henderson
,
15:47
Re: [Qemu-riscv] [RFC v2 24/24] WIP: Try to patch longer branches
,
Richard Henderson
,
15:40
Re: [Qemu-riscv] [RFC v2 23/24] WIP: Add missing instructions
,
Richard Henderson
,
15:31
Re: [Qemu-riscv] [RFC v2 14/24] riscv: tcg-target: Add branch and jump instructions
,
Richard Henderson
,
15:15
Re: [Qemu-riscv] [RFC v2 11/24] riscv: tcg-target: Add the mov and movi instruction
,
Richard Henderson
,
14:48
Re: [Qemu-riscv] [RFC v2 10/24] riscv: tcg-target: Add the relocation functions
,
Richard Henderson
,
14:38
Re: [Qemu-riscv] [RFC v2 08/24] riscv: tcg-target: Add the immediate encoders
,
Richard Henderson
,
14:36
Re: [Qemu-riscv] [RFC v2 07/24] riscv: tcg-target: Add support for the constraints
,
Richard Henderson
,
14:33
Re: [Qemu-riscv] [RFC v2 05/24] riscv: Add the tcg-target header file
,
Richard Henderson
,
14:29
Re: [Qemu-riscv] [Qemu-devel] [PATCH] riscv/cpu: use device_class_set_parent_realize
,
Palmer Dabbelt
,
13:51
November 27, 2018
Re: [Qemu-riscv] [Qemu-devel] [PATCH] riscv/cpu: use device_class_set_parent_realize
,
maozy
,
20:46
Re: [Qemu-riscv] [Qemu-devel] [PATCH] riscv/cpu: use device_class_set_parent_realize
,
Palmer Dabbelt
,
19:34
[Qemu-riscv] [PATCH v1 1/1] riscv: Ensure the kernel start address is correctly cast
,
Alistair Francis
,
19:34
Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 1/1] riscv: virt: Cast the initrd start address to target bit length
,
Alexander Graf
,
18:20
Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 1/1] riscv: virt: Cast the initrd start address to target bit length
,
Alexander Graf
,
18:20
Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 1/1] riscv: virt: Cast the initrd start address to target bit length
,
Alistair Francis
,
17:29
Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 1/1] riscv: virt: Cast the initrd start address to target bit length
,
Alistair Francis
,
17:25
Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 1/1] riscv: virt: Cast the initrd start address to target bit length
,
Alistair Francis
,
17:06
Re: [Qemu-riscv] [RFC v2 00/24] Add RISC-V TCG backend support
,
Alistair Francis
,
16:10
[Qemu-riscv] [RFC v2 24/24] WIP: Try to patch longer branches
,
Alistair Francis
,
16:10
[Qemu-riscv] [RFC v2 23/24] WIP: Add missing instructions
,
Alistair Francis
,
16:10
[Qemu-riscv] [RFC v2 22/24] configure: Add support for building RISC-V host
,
Alistair Francis
,
16:10
[Qemu-riscv] [RFC v2 21/24] dias: Add RISC-V support
,
Alistair Francis
,
16:09
[Qemu-riscv] [RFC v2 20/24] tcg: Add RISC-V cpu signal handler
,
Alistair Francis
,
16:09
[Qemu-riscv] [RFC v2 19/24] riscv: tcg-target: Add the target init code
,
Alistair Francis
,
16:09
[Qemu-riscv] [RFC v2 18/24] riscv: tcg-target: Add the prologue generation and register the JIT
,
Alistair Francis
,
16:09
[Qemu-riscv] [RFC v2 17/24] riscv: tcg-target: Add the out op decoder
,
Alistair Francis
,
16:09
[Qemu-riscv] [RFC v2 16/24] riscv: tcg-target: Add direct load and store instructions
,
Alistair Francis
,
16:09
[Qemu-riscv] [RFC v2 15/24] riscv: tcg-target: Add slowpath load and store instructions
,
Alistair Francis
,
16:09
[Qemu-riscv] [RFC v2 14/24] riscv: tcg-target: Add branch and jump instructions
,
Alistair Francis
,
16:08
[Qemu-riscv] [RFC v2 13/24] riscv: tcg-target: Add the out load and store instructions
,
Alistair Francis
,
16:08
[Qemu-riscv] [RFC v2 12/24] riscv: tcg-target: Add the extract instructions
,
Alistair Francis
,
16:08
[Qemu-riscv] [RFC v2 11/24] riscv: tcg-target: Add the mov and movi instruction
,
Alistair Francis
,
16:08
[Qemu-riscv] [RFC v2 09/24] riscv: tcg-target: Add the instruction emitters
,
Alistair Francis
,
16:08
[Qemu-riscv] [RFC v2 10/24] riscv: tcg-target: Add the relocation functions
,
Alistair Francis
,
16:08
[Qemu-riscv] [RFC v2 08/24] riscv: tcg-target: Add the immediate encoders
,
Alistair Francis
,
16:08
[Qemu-riscv] [RFC v2 07/24] riscv: tcg-target: Add support for the constraints
,
Alistair Francis
,
16:08
[Qemu-riscv] [RFC v2 06/24] riscv: Add the tcg target registers
,
Alistair Francis
,
16:07
[Qemu-riscv] [RFC v2 05/24] riscv: Add the tcg-target header file
,
Alistair Francis
,
16:07
[Qemu-riscv] [RFC v2 04/24] exec: Add RISC-V GCC poison macro
,
Alistair Francis
,
16:07
[Qemu-riscv] [RFC v2 03/24] linux-user: Add host dependency for RISC-V 64-bit
,
Alistair Francis
,
16:07
[Qemu-riscv] [RFC v2 02/24] linux-user: Add host dependency for RISC-V 32-bit
,
Alistair Francis
,
16:07
[Qemu-riscv] [RFC v2 01/24] elf.h: Add the RISCV ELF magic numbers
,
Alistair Francis
,
16:07
[Qemu-riscv] [RFC v2 00/24] Add RISC-V TCG backend support
,
Alistair Francis
,
16:06
[Qemu-riscv] Contribution procedures for RISC-V QEMU
,
Fabien Chouteau
,
08:40
Re: [Qemu-riscv] [Qemu-devel] [PATCH for-3.2 v7 0/6] Connect a PCIe host and graphics support to RISC-V
,
Andrea Bolognani
,
07:41
November 26, 2018
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 15/23] riscv: tcg-target: Add branch and jump instructions
,
Alistair Francis
,
17:59
Re: [Qemu-riscv] [Qemu-devel] [PATCH for-3.2 v7 0/6] Connect a PCIe host and graphics support to RISC-V
,
Guenter Roeck
,
16:33
Re: [Qemu-riscv] [Qemu-devel] [PATCH for-3.2 v7 0/6] Connect a PCIe host and graphics support to RISC-V
,
Palmer Dabbelt
,
14:35
Re: [Qemu-riscv] [Qemu-devel] [PATCH for-3.2] RISC-V: Deprecate hifive_e and hifive_u machines
,
Palmer Dabbelt
,
14:17
Re: [Qemu-riscv] [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe
,
Palmer Dabbelt
,
14:15
Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 1/1] riscv: virt: Cast the initrd start address to target bit length
,
Palmer Dabbelt
,
14:03
Re: [Qemu-riscv] [Qemu-devel] [PATCH] riscv/cpu: use device_class_set_parent_realize
,
Alistair Francis
,
11:05
Re: [Qemu-riscv] [PATCH for-3.2 v7 0/6] Connect a PCIe host and graphics support to RISC-V
,
Alistair Francis
,
11:04
[Qemu-riscv] [PATCH] riscv/cpu: use device_class_set_parent_realize
,
Mao Zhongyi
,
08:49
Re: [Qemu-riscv] [Qemu-devel] [PATCH] riscv/cpu: use device_class_set_parent_realize
,
Bastian Koppelmann
,
04:26
November 22, 2018
Re: [Qemu-riscv] [Qemu-devel] [PATCH for-3.2] RISC-V: Deprecate hifive_e and hifive_u machines
,
Thomas Huth
,
08:42
Re: [Qemu-riscv] [Qemu-devel] [PATCH for-3.1 1/2] MAINTAINERS: Any file with "riscv" in the name is a RISC-V file
,
Thomas Huth
,
08:42
Re: [Qemu-riscv] [PATCH for-3.2 v7 0/6] Connect a PCIe host and graphics support to RISC-V
,
Andrea Bolognani
,
05:59
November 21, 2018
Re: [Qemu-riscv] [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe
,
Alistair Francis
,
21:23
Re: [Qemu-riscv] [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe
,
Palmer Dabbelt
,
21:13
Re: [Qemu-riscv] [Qemu-devel] [PATCH for-3.1 2/2] MAINTAINERS: Mark RISC-V as Supported
,
Alistair Francis
,
21:10
Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 1/1] riscv: virt: Cast the initrd start address to target bit length
,
Alistair Francis
,
21:10
Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 1/1] riscv: virt: Cast the initrd start address to target bit length
,
Palmer Dabbelt
,
20:58
Re: [Qemu-riscv] [Qemu-devel] [PATCH for-3.1 1/2] MAINTAINERS: Any file with "riscv" in the name is a RISC-V file
,
Palmer Dabbelt
,
20:45
Re: [Qemu-riscv] [Qemu-devel] [PATCH for-3.1 1/2] MAINTAINERS: Any file with "riscv" in the name is a RISC-V file
,
Philippe Mathieu-Daudé
,
19:29
[Qemu-riscv] [PATCH for-3.2] RISC-V: Deprecate hifive_e and hifive_u machines
,
Palmer Dabbelt
,
18:55
[Qemu-riscv] [PATCH for-3.1 1/2] MAINTAINERS: Any file with "riscv" in the name is a RISC-V file
,
Palmer Dabbelt
,
18:55
[Qemu-riscv] [PATCH for-3.1 2/2] MAINTAINERS: Mark RISC-V as Supported
,
Palmer Dabbelt
,
18:55
Re: [Qemu-riscv] [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe
,
Logan Gunthorpe
,
18:26
Re: [Qemu-riscv] [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe
,
Guenter Roeck
,
18:10
Re: [Qemu-riscv] [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe
,
Palmer Dabbelt
,
17:36
[Qemu-riscv] [PATCH v1 1/1] riscv: virt: Cast the initrd start address to target bit length
,
Alistair Francis
,
17:35
Re: [Qemu-riscv] [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe
,
Alistair Francis
,
17:23
Re: [Qemu-riscv] [PATCH for-3.2 v7 6/6] hw/riscv/virt: Connect a VirtIO net PCIe device
,
Logan Gunthorpe
,
17:19
Re: [Qemu-riscv] [PATCH for-3.2 v7 6/6] hw/riscv/virt: Connect a VirtIO net PCIe device
,
Logan Gunthorpe
,
17:16
Re: [Qemu-riscv] [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe
,
Palmer Dabbelt
,
17:16
Re: [Qemu-riscv] [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe
,
Palmer Dabbelt
,
17:16
Re: [Qemu-riscv] [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe
,
Palmer Dabbelt
,
17:16
Re: [Qemu-riscv] [PATCH for-3.2 v7 6/6] hw/riscv/virt: Connect a VirtIO net PCIe device
,
Alistair Francis
,
17:14
Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe
,
Logan Gunthorpe
,
17:12
Re: [Qemu-riscv] [PATCH for-3.2 v7 6/6] hw/riscv/virt: Connect a VirtIO net PCIe device
,
Alistair Francis
,
17:11
Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe
,
Alistair Francis
,
17:10
Re: [Qemu-riscv] [PATCH for-3.2 v7 6/6] hw/riscv/virt: Connect a VirtIO net PCIe device
,
Logan Gunthorpe
,
17:07
Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe
,
Logan Gunthorpe
,
17:01
Re: [Qemu-riscv] [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe
,
Alistair Francis
,
17:01
Re: [Qemu-riscv] [PATCH for-3.2 v7 6/6] hw/riscv/virt: Connect a VirtIO net PCIe device
,
Alistair Francis
,
16:56
Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe
,
Alistair Francis
,
16:55
Re: [Qemu-riscv] [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe
,
Alistair Francis
,
16:50
Re: [Qemu-riscv] [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe
,
Palmer Dabbelt
,
16:37
Re: [Qemu-riscv] [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe
,
Palmer Dabbelt
,
16:34
Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe
,
Alistair Francis
,
14:52
Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe
,
Logan Gunthorpe
,
14:25
Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe
,
Alistair Francis
,
14:22
Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe
,
Logan Gunthorpe
,
14:21
Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe
,
Logan Gunthorpe
,
14:19
Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe
,
Alistair Francis
,
14:19
Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe
,
Alistair Francis
,
14:17
Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe
,
Logan Gunthorpe
,
14:15
Re: [Qemu-riscv] [PATCH for-3.2 v7 6/6] hw/riscv/virt: Connect a VirtIO net PCIe device
,
Logan Gunthorpe
,
14:12
Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe
,
Logan Gunthorpe
,
14:09
Re: [Qemu-riscv] [Qemu-devel] [PATCH 1/2] riscv: virt: Fix pcie memory ranges
,
Guenter Roeck
,
14:05
Re: [Qemu-riscv] [Qemu-devel] [PATCH 1/2] riscv: virt: Fix pcie memory ranges
,
Guenter Roeck
,
14:05
Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe
,
Alistair Francis
,
14:03
Re: [Qemu-riscv] [PATCH for-3.2 v7 1/6] hw/riscv/virt: Increase the number of interrupts
,
Logan Gunthorpe
,
14:02
Re: [Qemu-riscv] [PATCH for-3.2 v7 1/6] hw/riscv/virt: Increase the number of interrupts
,
Alistair Francis
,
14:00
Re: [Qemu-riscv] [PATCH for-3.2 v7 1/6] hw/riscv/virt: Increase the number of interrupts
,
Logan Gunthorpe
,
13:56
Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe
,
Logan Gunthorpe
,
13:55
Re: [Qemu-riscv] [PATCH for-3.2 v7 1/6] hw/riscv/virt: Increase the number of interrupts
,
Alistair Francis
,
13:50
Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe
,
Logan Gunthorpe
,
13:50
Re: [Qemu-riscv] [PATCH for-3.2 v7 1/6] hw/riscv/virt: Increase the number of interrupts
,
Logan Gunthorpe
,
13:46
Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe
,
Guenter Roeck
,
13:36
Re: [Qemu-riscv] [PATCH for-3.2 v7 6/6] hw/riscv/virt: Connect a VirtIO net PCIe device
,
Alistair Francis
,
13:35
Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe
,
Alistair Francis
,
13:33
Re: [Qemu-riscv] [PATCH for-3.2 v7 3/6] hw/riscv/virt: Connect the gpex PCIe
,
Alistair Francis
,
13:22
Re: [Qemu-riscv] [PATCH for-3.2 v7 1/6] hw/riscv/virt: Increase the number of interrupts
,
Alistair Francis
,
13:18
Re: [Qemu-riscv] [PATCH for-3.2 v7 3/6] hw/riscv/virt: Connect the gpex PCIe
,
Logan Gunthorpe
,
13:17
Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe
,
Logan Gunthorpe
,
13:17
Re: [Qemu-riscv] [PATCH for-3.2 v7 4/6] riscv: Enable VGA and PCIE_VGA
,
Logan Gunthorpe
,
13:17
Re: [Qemu-riscv] [PATCH for-3.2 v7 6/6] hw/riscv/virt: Connect a VirtIO net PCIe device
,
Logan Gunthorpe
,
13:16
Re: [Qemu-riscv] [PATCH for-3.2 v7 2/6] hw/riscv/virt: Adjust memory layout spacing
,
Logan Gunthorpe
,
13:04
Re: [Qemu-riscv] [PATCH for-3.2 v7 1/6] hw/riscv/virt: Increase the number of interrupts
,
Logan Gunthorpe
,
13:04
[Qemu-riscv] [PATCH for-3.2 v7 6/6] hw/riscv/virt: Connect a VirtIO net PCIe device
,
Alistair Francis
,
12:03
[Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe
,
Alistair Francis
,
12:03
[Qemu-riscv] [PATCH for-3.2 v7 2/6] hw/riscv/virt: Adjust memory layout spacing
,
Alistair Francis
,
12:03
[Qemu-riscv] [PATCH for-3.2 v7 4/6] riscv: Enable VGA and PCIE_VGA
,
Alistair Francis
,
12:03
[Qemu-riscv] [PATCH for-3.2 v7 1/6] hw/riscv/virt: Increase the number of interrupts
,
Alistair Francis
,
12:03
[Qemu-riscv] [PATCH for-3.2 v7 3/6] hw/riscv/virt: Connect the gpex PCIe
,
Alistair Francis
,
12:02
[Qemu-riscv] [PATCH for-3.2 v7 0/6] Connect a PCIe host and graphics support to RISC-V
,
Alistair Francis
,
12:02
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 11/23] riscv: tcg-target: Add the relocation functions
,
Richard Henderson
,
12:01
Re: [Qemu-riscv] [Qemu-devel] [PATCH 1/2] riscv: virt: Fix pcie memory ranges
,
Alistair Francis
,
11:15
Re: [Qemu-riscv] [Qemu-devel] [PATCH 1/2] riscv: virt: Fix pcie memory ranges
,
Alistair Francis
,
11:15
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 11/23] riscv: tcg-target: Add the relocation functions
,
Palmer Dabbelt
,
10:53
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 15/23] riscv: tcg-target: Add branch and jump instructions
,
Richard Henderson
,
02:49
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 16/23] riscv: tcg-target: Add slowpath load and store instructions
,
Richard Henderson
,
02:49
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 11/23] riscv: tcg-target: Add the relocation functions
,
Richard Henderson
,
02:25
November 20, 2018
Re: [Qemu-riscv] [Qemu-devel] [PATCH 1/2] riscv: virt: Fix pcie memory ranges
,
Guenter Roeck
,
23:19
Re: [Qemu-riscv] [Qemu-devel] [PATCH 1/2] riscv: virt: Fix pcie memory ranges
,
Guenter Roeck
,
20:54
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 11/23] riscv: tcg-target: Add the relocation functions
,
Alistair Francis
,
20:15
Re: [Qemu-riscv] [Qemu-devel] [PATCH 2/2] riscv: virt: Fix interrupt mapping
,
Alistair Francis
,
19:49
Re: [Qemu-riscv] [Qemu-devel] [PATCH 1/2] riscv: virt: Fix pcie memory ranges
,
Alistair Francis
,
19:43
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 16/23] riscv: tcg-target: Add slowpath load and store instructions
,
Alistair Francis
,
19:19
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 15/23] riscv: tcg-target: Add branch and jump instructions
,
Alistair Francis
,
18:50
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 20/23] riscv: tcg-target: Add the target init code
,
Alistair Francis
,
18:27
[Qemu-riscv] [PATCH 1/2] riscv: virt: Fix pcie memory ranges
,
Guenter Roeck
,
18:21
[Qemu-riscv] [PATCH 2/2] riscv: virt: Fix interrupt mapping
,
Guenter Roeck
,
18:21
[Qemu-riscv] No RISC-V Patches this Week
,
Palmer Dabbelt
,
18:11
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 17/23] riscv: tcg-target: Add direct load and store instructions
,
Richard Henderson
,
01:58
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 20/23] riscv: tcg-target: Add the target init code
,
Richard Henderson
,
01:55
November 19, 2018
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 17/23] riscv: tcg-target: Add direct load and store instructions
,
Alistair Francis
,
18:07
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 20/23] riscv: tcg-target: Add the target init code
,
Alistair Francis
,
18:05
Re: [Qemu-riscv] [PULL] RISC-V Patches for 3.1-rc2
,
Peter Maydell
,
05:23
November 16, 2018
[Qemu-riscv] [PULL 4/4] RISC-V: Respect fences for user-only emulators
,
Palmer Dabbelt
,
16:31
[Qemu-riscv] [PULL 3/4] target/riscv: Fix sfence.vm/a both available in any priv version
,
Palmer Dabbelt
,
16:31
[Qemu-riscv] [PULL] RISC-V Patches for 3.1-rc2
,
Palmer Dabbelt
,
16:31
[Qemu-riscv] [PULL 2/4] target/riscv: Fix FCLASS_D being treated as RV64 only
,
Palmer Dabbelt
,
16:31
[Qemu-riscv] [PULL 1/4] hw/riscv/virt: Free the test device tree node name
,
Palmer Dabbelt
,
16:31
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 23/23] configure: Add support for building RISC-V host
,
Richard Henderson
,
12:31
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 22/23] dias: Add RISC-V support
,
Richard Henderson
,
12:30
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 21/23] tcg: Add RISC-V cpu signal handler
,
Richard Henderson
,
12:29
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 21/23] tcg: Add RISC-V cpu signal handler
,
Richard Henderson
,
12:28
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 20/23] riscv: tcg-target: Add the target init code
,
Richard Henderson
,
12:26
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 19/23] riscv: tcg-target: Add the prologue generation
,
Richard Henderson
,
12:26
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 18/23] riscv: tcg-target: Add the out op decoder
,
Richard Henderson
,
12:23
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 05/23] riscv: Add the tcg-target header file
,
Richard Henderson
,
12:21
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 17/23] riscv: tcg-target: Add direct load and store instructions
,
Richard Henderson
,
12:10
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 16/23] riscv: tcg-target: Add slowpath load and store instructions
,
Richard Henderson
,
04:24
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 15/23] riscv: tcg-target: Add branch and jump instructions
,
Richard Henderson
,
04:14
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 14/23] riscv: tcg-target: Add the out load and store instructions
,
Richard Henderson
,
03:59
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 13/23] riscv: tcg-target: Add the extract instructions
,
Richard Henderson
,
03:57
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 12/23] riscv: tcg-target: Add the mov and movi instruction
,
Richard Henderson
,
03:55
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 11/23] riscv: tcg-target: Add the relocation functions
,
Richard Henderson
,
03:34
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 00/23] Add RISC-V TCG backend support
,
no-reply
,
03:32
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 10/23] riscv: tcg-target: Add the instruction emitters
,
Richard Henderson
,
03:27
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 09/23] riscv: tcg-target: Add the immediate encoders
,
Richard Henderson
,
03:26
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 08/23] riscv: tcg-target: Add support for the constraints
,
Richard Henderson
,
03:13
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 07/23] riscv: tcg-target: Regiser the JIT
,
Richard Henderson
,
02:59
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 06/23] riscv: Add the tcg target registers
,
Richard Henderson
,
02:58
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 03/23] linux-user: Add host dependency for RISC-V 64-bit
,
Richard Henderson
,
02:57
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 05/23] riscv: Add the tcg-target header file
,
Richard Henderson
,
02:57
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 02/23] linux-user: Add host dependency for RISC-V 32-bit
,
Richard Henderson
,
02:48
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 04/23] exec: Add RISC-V GCC poison macro
,
Richard Henderson
,
02:48
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 02/23] linux-user: Add host dependency for RISC-V 32-bit
,
Richard Henderson
,
02:47
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 01/23] elf.h: Add the RISCV ELF magic numbers
,
Richard Henderson
,
02:46
November 15, 2018
[Qemu-riscv] [RFC v1 23/23] configure: Add support for building RISC-V host
,
Alistair Francis
,
17:38
[Qemu-riscv] [RFC v1 22/23] dias: Add RISC-V support
,
Alistair Francis
,
17:37
[Qemu-riscv] [RFC v1 21/23] tcg: Add RISC-V cpu signal handler
,
Alistair Francis
,
17:37
[Qemu-riscv] [RFC v1 20/23] riscv: tcg-target: Add the target init code
,
Alistair Francis
,
17:37
[Qemu-riscv] [RFC v1 19/23] riscv: tcg-target: Add the prologue generation
,
Alistair Francis
,
17:37
[Qemu-riscv] [RFC v1 18/23] riscv: tcg-target: Add the out op decoder
,
Alistair Francis
,
17:37
[Qemu-riscv] [RFC v1 17/23] riscv: tcg-target: Add direct load and store instructions
,
Alistair Francis
,
17:36
[Qemu-riscv] [RFC v1 16/23] riscv: tcg-target: Add slowpath load and store instructions
,
Alistair Francis
,
17:36
[Qemu-riscv] [RFC v1 15/23] riscv: tcg-target: Add branch and jump instructions
,
Alistair Francis
,
17:36
[Qemu-riscv] [RFC v1 14/23] riscv: tcg-target: Add the out load and store instructions
,
Alistair Francis
,
17:36
[Qemu-riscv] [RFC v1 13/23] riscv: tcg-target: Add the extract instructions
,
Alistair Francis
,
17:36
[Qemu-riscv] [RFC v1 12/23] riscv: tcg-target: Add the mov and movi instruction
,
Alistair Francis
,
17:35
[Qemu-riscv] [RFC v1 10/23] riscv: tcg-target: Add the instruction emitters
,
Alistair Francis
,
17:35
[Qemu-riscv] [RFC v1 11/23] riscv: tcg-target: Add the relocation functions
,
Alistair Francis
,
17:35
[Qemu-riscv] [RFC v1 09/23] riscv: tcg-target: Add the immediate encoders
,
Alistair Francis
,
17:35
[Qemu-riscv] [RFC v1 08/23] riscv: tcg-target: Add support for the constraints
,
Alistair Francis
,
17:35
[Qemu-riscv] [RFC v1 07/23] riscv: tcg-target: Regiser the JIT
,
Alistair Francis
,
17:35
[Qemu-riscv] [RFC v1 06/23] riscv: Add the tcg target registers
,
Alistair Francis
,
17:35
[Qemu-riscv] [RFC v1 05/23] riscv: Add the tcg-target header file
,
Alistair Francis
,
17:34
[Qemu-riscv] [RFC v1 04/23] exec: Add RISC-V GCC poison macro
,
Alistair Francis
,
17:34
[Qemu-riscv] [RFC v1 03/23] linux-user: Add host dependency for RISC-V 64-bit
,
Alistair Francis
,
17:34
[Qemu-riscv] [RFC v1 02/23] linux-user: Add host dependency for RISC-V 32-bit
,
Alistair Francis
,
17:34
[Qemu-riscv] [RFC v1 01/23] elf.h: Add the RISCV ELF magic numbers
,
Alistair Francis
,
17:34
[Qemu-riscv] [RFC v1 00/23] Add RISC-V TCG backend support
,
Alistair Francis
,
17:34
November 14, 2018
Re: [Qemu-riscv] [Qemu-devel] [PR RFC] RISC-V Patches for 3.1-rc2
,
Michael Clark
,
02:24
Re: [Qemu-riscv] [Qemu-devel] [PULL 4/4] RISC-V: Respect fences for user-only emulators
,
Michael Clark
,
02:24
November 13, 2018
[Qemu-riscv] [PULL 4/4] RISC-V: Respect fences for user-only emulators
,
Palmer Dabbelt
,
18:51
[Qemu-riscv] [PULL 3/4] target/riscv: Fix sfence.vm/a both available in any priv version
,
Palmer Dabbelt
,
18:51
[Qemu-riscv] [PULL 1/4] hw/riscv/virt: Free the test device tree node name
,
Palmer Dabbelt
,
18:51
[Qemu-riscv] [PULL 2/4] target/riscv: Fix FCLASS_D being treated as RV64 only
,
Palmer Dabbelt
,
18:51
[Qemu-riscv] [PR RFC] RISC-V Patches for 3.1-rc2
,
Palmer Dabbelt
,
18:51
Re: [Qemu-riscv] [Qemu-devel] [PATCH 1/2] target/riscv: Fix FCLASS_D being treated as RV64 only
,
Alistair Francis
,
15:11
Re: [Qemu-riscv] [Qemu-devel] [PATCH 2/2] target/riscv: Fix sfence.vm/a both available in any priv version
,
Alistair Francis
,
15:11
Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 0/5] Connect a PCIe host and graphics support to RISC-V
,
Andrea Bolognani
,
10:53
November 10, 2018
Re: [Qemu-riscv] [PATCH for 3.1] RISC-V: Respect fences for user-only emulators
,
Richard Henderson
,
03:38
November 09, 2018
Re: [Qemu-riscv] [Qemu-devel] [PATCH for 3.1] RISC-V: Respect fences for user-only emulators
,
Alistair Francis
,
17:11
[Qemu-riscv] [PATCH for 3.1] RISC-V: Respect fences for user-only emulators
,
Palmer Dabbelt
,
14:20
[Qemu-riscv] [PATCH for 3.1] RISC-V: Respect fences for user-only emulators
,
Palmer Dabbelt
,
14:20
Re: [Qemu-riscv] [Qemu-devel] [PULL] A Single RISC-V Patch for 3.1-rc1
,
Palmer Dabbelt
,
14:01
Re: [Qemu-riscv] [Qemu-devel] [PULL] A Single RISC-V Patch for 3.1-rc1
,
Peter Maydell
,
05:54
Re: [Qemu-riscv] [Qemu-devel] [PATCH 0/2] target/riscv: Bugfixes found in decodetree conversion
,
Richard Henderson
,
01:14
November 08, 2018
Re: [Qemu-riscv] [Qemu-devel] [PATCH 0/2] target/riscv: Bugfixes found in decodetree conversion
,
Palmer Dabbelt
,
14:12
Re: [Qemu-riscv] [PATCH for 3.1 v1 1/1] hw/riscv/virt: Free the test device tree node name
,
Palmer Dabbelt
,
14:04
Re: [Qemu-riscv] [Qemu-devel] [PULL] A Single RISC-V Patch for 3.1-rc1
,
Palmer Dabbelt
,
13:53
Re: [Qemu-riscv] [PATCH for 3.1 v1 1/1] hw/riscv/virt: Free the test device tree node name
,
Palmer Dabbelt
,
13:51
Re: [Qemu-riscv] [Qemu-devel] [PULL] A Single RISC-V Patch for 3.1-rc1
,
Alistair Francis
,
13:41
Re: [Qemu-riscv] [PATCH for 3.1 v1 1/1] hw/riscv/virt: Free the test device tree node name
,
Alistair Francis
,
13:38
[Qemu-riscv] [PULL] A Single RISC-V Patch for 3.1-rc1
,
Palmer Dabbelt
,
13:33
[Qemu-riscv] [PULL] riscv: spike: Fix memory leak in the board init
,
Palmer Dabbelt
,
13:33
Re: [Qemu-riscv] [Qemu-devel] [PATCH 0/2] target/riscv: Bugfixes found in decodetree conversion
,
Bastian Koppelmann
,
12:29
Re: [Qemu-riscv] [Qemu-devel] [PATCH 0/2] target/riscv: Bugfixes found in decodetree conversion
,
Richard Henderson
,
10:54
Re: [Qemu-riscv] [Qemu-devel] [PATCH 1/2] target/riscv: Fix FCLASS_D being treated as RV64 only
,
Richard Henderson
,
10:47
Re: [Qemu-riscv] [Qemu-devel] [PATCH 2/2] target/riscv: Fix sfence.vm/a both available in any priv version
,
Richard Henderson
,
10:44
[Qemu-riscv] [PATCH 2/2] target/riscv: Fix sfence.vm/a both available in any priv version
,
Bastian Koppelmann
,
07:07
[Qemu-riscv] [PATCH 1/2] target/riscv: Fix FCLASS_D being treated as RV64 only
,
Bastian Koppelmann
,
07:07
[Qemu-riscv] [PATCH 0/2] target/riscv: Bugfixes found in decodetree conversion
,
Bastian Koppelmann
,
07:07
November 07, 2018
Re: [Qemu-riscv] [PATCH for 3.1 v1 1/1] hw/riscv/virt: Free the test device tree node name
,
Palmer Dabbelt
,
21:38
[Qemu-riscv] [PATCH for 3.1 v1 1/1] hw/riscv/virt: Free the test device tree node name
,
Alistair Francis
,
16:52
Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 0/5] Connect a PCIe host and graphics support to RISC-V
,
Alistair Francis
,
16:48
Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 2/5] hw/riscv/virt: Connect the gpex PCIe
,
Alistair Francis
,
16:46
November 06, 2018
Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 26/35] target/riscv: Remove shift and slt insn manual decoding
,
Palmer Dabbelt
,
19:57
Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 1/1] riscv: spike: Fix memory leak in the board init
,
Palmer Dabbelt
,
18:59
Re: [Qemu-riscv] [PATCH v1 1/1] riscv: spike: Fix memory leak in the board init
,
Peter Maydell
,
08:29
Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 2/5] hw/riscv/virt: Connect the gpex PCIe
,
Bin Meng
,
01:45
November 05, 2018
[Qemu-riscv] [PATCH v1 1/1] riscv: spike: Fix memory leak in the board init
,
Alistair Francis
,
14:49
Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 2/5] hw/riscv/virt: Connect the gpex PCIe
,
Alistair Francis
,
14:47
Re: [Qemu-riscv] [Qemu-devel] coverity-spotted memory leak in hw/riscv/spike.c
,
Alistair Francis
,
12:54
Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 26/35] target/riscv: Remove shift and slt insn manual decoding
,
Bastian Koppelmann
,
12:11
Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 2/5] hw/riscv/virt: Connect the gpex PCIe
,
Bin Meng
,
09:01
[Qemu-riscv] coverity-spotted memory leak in hw/riscv/spike.c
,
Peter Maydell
,
08:42
November 02, 2018
Re: [Qemu-riscv] [PULL] RISC-V Patches for the 3.1 Soft Freeze, Part 2
,
Peter Maydell
,
12:00
Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 00/35] target/riscv: Convert to decodetree
,
no-reply
,
12:00
November 01, 2018
[Qemu-riscv] [PULL 3/3] Add address@hidden as the RISC-V list
,
Palmer Dabbelt
,
19:55
[Qemu-riscv] [PULL] RISC-V Patches for the 3.1 Soft Freeze, Part 2
,
Palmer Dabbelt
,
19:55
[Qemu-riscv] [PULL 2/3] Add Alistair as a RISC-V Maintainer
,
Palmer Dabbelt
,
19:55
[Qemu-riscv] [PULL 1/3] target/riscv/pmp.c: pmpcfg_csr_read returns bogus value on RV64
,
Palmer Dabbelt
,
19:55
Re: [Qemu-riscv] [PATCH v3 26/35] target/riscv: Remove shift and slt insn manual decoding
,
Palmer Dabbelt
,
11:59
Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 0/5] Connect a PCIe host and graphics support to RISC-V
,
Andrea Bolognani
,
04:20
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