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[Qemu-riscv] [RFC v3 09/24] riscv: tcg-target: Add the immediate encoder
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From: |
Alistair Francis |
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Subject: |
[Qemu-riscv] [RFC v3 09/24] riscv: tcg-target: Add the immediate encoders |
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Date: |
Sat, 8 Dec 2018 00:47:35 +0000 |
Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
tcg/riscv/tcg-target.inc.c | 90 ++++++++++++++++++++++++++++++++++++++
1 file changed, 90 insertions(+)
diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
index af1d2c235a..c385ff68ae 100644
--- a/tcg/riscv/tcg-target.inc.c
+++ b/tcg/riscv/tcg-target.inc.c
@@ -284,3 +284,93 @@ typedef enum {
OPC_FENCE = 0x0000000f,
} RISCVInsn;
+
+/*
+ * RISC-V immediate and instruction encoders (excludes 16-bit RVC)
+ */
+
+/* Type-R */
+
+static int32_t encode_r(RISCVInsn opc, TCGReg rd, TCGReg rs1, TCGReg rs2)
+{
+ return opc | (rd & 0x1f) << 7 | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20;
+}
+
+/* Type-I */
+
+static int32_t encode_imm12(uint32_t imm)
+{
+ return (imm & 0xfff) << 20;
+}
+
+static int32_t encode_i(RISCVInsn opc, TCGReg rd, TCGReg rs1, uint32_t imm)
+{
+ return opc | (rd & 0x1f) << 7 | (rs1 & 0x1f) << 15 | encode_imm12(imm);
+}
+
+/* Type-S */
+
+static int32_t encode_simm12(uint32_t imm)
+{
+ int32_t ret = 0;
+
+ ret |= (imm & 0xFE0) << 20;
+ ret |= (imm & 0x1F) << 7;
+
+ return ret;
+}
+
+static int32_t encode_s(RISCVInsn opc, TCGReg rs1, TCGReg rs2, uint32_t imm)
+{
+ return opc | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20 | encode_simm12(imm);
+}
+
+/* Type-SB */
+
+static int32_t encode_sbimm12(uint32_t imm)
+{
+ int32_t ret = 0;
+
+ ret |= (imm & 0x1000) << 19;
+ ret |= (imm & 0x7e0) << 20;
+ ret |= (imm & 0x1e) << 7;
+ ret |= (imm & 0x800) >> 4;
+
+ return ret;
+}
+
+static int32_t encode_sb(RISCVInsn opc, TCGReg rs1, TCGReg rs2, uint32_t imm)
+{
+ return opc | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20 | encode_sbimm12(imm);
+}
+
+/* Type-U */
+
+static int32_t encode_uimm20(uint32_t imm)
+{
+ return imm & 0xfffff000;
+}
+
+static int32_t encode_u(RISCVInsn opc, TCGReg rd, uint32_t imm)
+{
+ return opc | (rd & 0x1f) << 7 | encode_uimm20(imm);
+}
+
+/* Type-UJ */
+
+static int32_t encode_ujimm20(uint32_t imm)
+{
+ int32_t ret = 0;
+
+ ret |= (imm & 0x0007fe) << (21 - 1);
+ ret |= (imm & 0x000800) << (20 - 11);
+ ret |= (imm & 0x0ff000) << (12 - 12);
+ ret |= (imm & 0x100000) << (31 - 20);
+
+ return ret;
+}
+
+static int32_t encode_uj(RISCVInsn opc, TCGReg rd, uint32_t imm)
+{
+ return opc | (rd & 0x1f) << 7 | encode_ujimm20(imm);
+}
--
2.19.1
- [Qemu-riscv] [RFC v3 02/24] linux-user: Add host dependency for RISC-V 32-bit, (continued)
- [Qemu-riscv] [RFC v3 02/24] linux-user: Add host dependency for RISC-V 32-bit, Alistair Francis, 2018/12/07
- [Qemu-riscv] [RFC v3 03/24] linux-user: Add host dependency for RISC-V 64-bit, Alistair Francis, 2018/12/07
- [Qemu-riscv] [RFC v3 04/24] linux-user: riscv: Fix compile failure on riscv32 hosts, Alistair Francis, 2018/12/07
- [Qemu-riscv] [RFC v3 05/24] exec: Add RISC-V GCC poison macro, Alistair Francis, 2018/12/07
- [Qemu-riscv] [RFC v3 06/24] riscv: Add the tcg-target header file, Alistair Francis, 2018/12/07
- [Qemu-riscv] [RFC v3 07/24] riscv: Add the tcg target registers, Alistair Francis, 2018/12/07
- [Qemu-riscv] [RFC v3 08/24] riscv: tcg-target: Add support for the constraints, Alistair Francis, 2018/12/07
- [Qemu-riscv] [RFC v3 09/24] riscv: tcg-target: Add the immediate encoders,
Alistair Francis <=
- [Qemu-riscv] [RFC v3 10/24] riscv: tcg-target: Add the instruction emitters, Alistair Francis, 2018/12/07
- [Qemu-riscv] [RFC v3 11/24] riscv: tcg-target: Add the relocation functions, Alistair Francis, 2018/12/07
- [Qemu-riscv] [RFC v3 12/24] riscv: tcg-target: Add the mov and movi instruction, Alistair Francis, 2018/12/07
- [Qemu-riscv] [RFC v3 13/24] riscv: tcg-target: Add the extract instructions, Alistair Francis, 2018/12/07
- [Qemu-riscv] [RFC v3 14/24] riscv: tcg-target: Add the out load and store instructions, Alistair Francis, 2018/12/07
- [Qemu-riscv] [RFC v3 15/24] riscv: tcg-target: Add the add2 and sub2 instructions, Alistair Francis, 2018/12/07
- [Qemu-riscv] [RFC v3 16/24] riscv: tcg-target: Add branch and jump instructions, Alistair Francis, 2018/12/07
- [Qemu-riscv] [RFC v3 17/24] riscv: tcg-target: Add slowpath load and store instructions, Alistair Francis, 2018/12/07