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Re: [Qemu-riscv] [RFC v3 19/24] riscv: tcg-target: Add the out op decode
From: |
Richard Henderson |
Subject: |
Re: [Qemu-riscv] [RFC v3 19/24] riscv: tcg-target: Add the out op decoder |
Date: |
Tue, 11 Dec 2018 16:44:56 -0600 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.3.1 |
On 12/10/18 11:56 AM, Richard Henderson wrote:
> On 12/7/18 6:49 PM, Alistair Francis wrote:
>> + case INDEX_op_neg_i64:
>> + tcg_out_opc_imm(s, OPC_SUB, a0, TCG_REG_ZERO, a1);
>
> tcg_out_opc_reg.
>
>> + case INDEX_op_mulsh_i32:
>> + case INDEX_op_mulsh_i64:
>> + tcg_out_opc_imm(s, OPC_MULH, a0, a1, a2);
>> + break;
>> +
>> + case INDEX_op_muluh_i32:
>> + case INDEX_op_muluh_i64:
>> + tcg_out_opc_imm(s, OPC_MULHU, a0, a1, a2);
>> + break;
>
> Likewise.
Incidentally, catching these sorts of errors is why tcg/s390 puts the format of
the insn into the enum. E.g.
/* Emit an opcode with "type-checking" of the format. */
#define tcg_out_insn(S, FMT, OP, ...) \
glue(tcg_out_insn_,FMT)(S, glue(glue(FMT,_),OP), ## __VA_ARGS__)
tcg_out_insn(s, RR, AR, a0, a2);
tcg_out_insn(s, RRE, AGR, TCG_TMP0, index);
/* All of the following instructions are prefixed with their instruction
format... */
typedef enum S390Opcode {
...
RR_AR = 0x1a,
RRE_AGR = 0xb908,
I do something similar for tcg/aarch64, although that's more complicated due to
the wide variety of formats.
Whether you go back and retro-fit this scheme to your existing patch set is up
to you. But I think it could be worthwhile.
r~
- [Qemu-riscv] [RFC v3 15/24] riscv: tcg-target: Add the add2 and sub2 instructions, (continued)
- [Qemu-riscv] [RFC v3 15/24] riscv: tcg-target: Add the add2 and sub2 instructions, Alistair Francis, 2018/12/07
- [Qemu-riscv] [RFC v3 16/24] riscv: tcg-target: Add branch and jump instructions, Alistair Francis, 2018/12/07
- [Qemu-riscv] [RFC v3 17/24] riscv: tcg-target: Add slowpath load and store instructions, Alistair Francis, 2018/12/07
- [Qemu-riscv] [RFC v3 18/24] riscv: tcg-target: Add direct load and store instructions, Alistair Francis, 2018/12/07
- [Qemu-riscv] [RFC v3 19/24] riscv: tcg-target: Add the out op decoder, Alistair Francis, 2018/12/07
- [Qemu-riscv] [RFC v3 20/24] riscv: tcg-target: Add the prologue generation and register the JIT, Alistair Francis, 2018/12/07
- [Qemu-riscv] [RFC v3 21/24] riscv: tcg-target: Add the target init code, Alistair Francis, 2018/12/07
- [Qemu-riscv] [RFC v3 22/24] tcg: Add RISC-V cpu signal handler, Alistair Francis, 2018/12/07
- [Qemu-riscv] [RFC v3 23/24] dias: Add RISC-V support, Alistair Francis, 2018/12/07
- [Qemu-riscv] [RFC v3 24/24] configure: Add support for building RISC-V host, Alistair Francis, 2018/12/07
- Re: [Qemu-riscv] [Qemu-devel] [RFC v3 00/24] Add RISC-V TCG backend support, no-reply, 2018/12/07