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Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 00/23] Add RISC-V TCG backend su
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Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 00/23] Add RISC-V TCG backend support |
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Date: |
Wed, 12 Dec 2018 18:48:59 -0800 (PST) |
Patchew URL: https://patchew.org/QEMU/address@hidden/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: address@hidden
Subject: [Qemu-devel] [PATCH v1 00/23] Add RISC-V TCG backend support
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
failed=1
echo
fi
n=$((n+1))
done
exit $failed
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
9b5c932 configure: Add support for building RISC-V host
fb15898 dias: Add RISC-V support
00c84d1 tcg: Add RISC-V cpu signal handler
6add641 riscv: tcg-target: Add the target init code
1558363 riscv: tcg-target: Add the prologue generation and register the JIT
eb2e81d riscv: tcg-target: Add the out op decoder
3810670 riscv: tcg-target: Add direct load and store instructions
3f9c9cb riscv: tcg-target: Add slowpath load and store instructions
effb6ef riscv: tcg-target: Add branch and jump instructions
6a4e141 riscv: tcg-target: Add the add2 and sub2 instructions
b275d63 riscv: tcg-target: Add the out load and store instructions
6739758 riscv: tcg-target: Add the extract instructions
5949cfc riscv: tcg-target: Add the mov and movi instruction
d304333 riscv: tcg-target: Add the relocation functions
417d704 riscv: tcg-target: Add the instruction emitters
0df8498 riscv: tcg-target: Add the immediate encoders
78dfa82 riscv: tcg-target: Add support for the constraints
de25c73 riscv: Add the tcg target registers
24cb807 riscv: Add the tcg-target header file
bc2a324 exec: Add RISC-V GCC poison macro
2d2a64a linux-user: Add host dependency for RISC-V 64-bit
19d241f linux-user: Add host dependency for RISC-V 32-bit
0bf04f5 elf.h: Add the RISCV ELF magic numbers
=== OUTPUT BEGIN ===
Checking PATCH 1/23: elf.h: Add the RISCV ELF magic numbers...
Checking PATCH 2/23: linux-user: Add host dependency for RISC-V 32-bit...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#24:
new file mode 100644
total: 0 errors, 1 warnings, 18 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 3/23: linux-user: Add host dependency for RISC-V 64-bit...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#24:
new file mode 100644
total: 0 errors, 1 warnings, 18 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 4/23: exec: Add RISC-V GCC poison macro...
Checking PATCH 5/23: riscv: Add the tcg-target header file...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#24:
new file mode 100644
WARNING: architecture specific defines should be avoided
#56: FILE: tcg/riscv/tcg-target.h:28:
+#if __riscv_xlen == 32
total: 0 errors, 2 warnings, 182 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 6/23: riscv: Add the tcg target registers...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#12:
new file mode 100644
total: 0 errors, 1 warnings, 118 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 7/23: riscv: tcg-target: Add support for the constraints...
Checking PATCH 8/23: riscv: tcg-target: Add the immediate encoders...
Checking PATCH 9/23: riscv: tcg-target: Add the instruction emitters...
Checking PATCH 10/23: riscv: tcg-target: Add the relocation functions...
Checking PATCH 11/23: riscv: tcg-target: Add the mov and movi instruction...
Checking PATCH 12/23: riscv: tcg-target: Add the extract instructions...
Checking PATCH 13/23: riscv: tcg-target: Add the out load and store
instructions...
Checking PATCH 14/23: riscv: tcg-target: Add the add2 and sub2 instructions...
Checking PATCH 15/23: riscv: tcg-target: Add branch and jump instructions...
Checking PATCH 16/23: riscv: tcg-target: Add slowpath load and store
instructions...
Checking PATCH 17/23: riscv: tcg-target: Add direct load and store
instructions...
ERROR: spaces required around that '*' (ctx:WxV)
#74: FILE: tcg/riscv/tcg-target.inc.c:1192:
+ tcg_insn_unit *label_ptr[1];
^
ERROR: spaces required around that '*' (ctx:WxV)
#145: FILE: tcg/riscv/tcg-target.inc.c:1263:
+ tcg_insn_unit *label_ptr[1];
^
total: 2 errors, 0 warnings, 161 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 18/23: riscv: tcg-target: Add the out op decoder...
Checking PATCH 19/23: riscv: tcg-target: Add the prologue generation and
register the JIT...
Checking PATCH 20/23: riscv: tcg-target: Add the target init code...
Checking PATCH 21/23: tcg: Add RISC-V cpu signal handler...
Checking PATCH 22/23: dias: Add RISC-V support...
WARNING: architecture specific defines should be avoided
#22: FILE: disas.c:526:
+#if defined(_ILP32) || (__riscv_xlen == 32)
total: 0 errors, 1 warnings, 16 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 23/23: configure: Add support for building RISC-V host...
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/address@hidden/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to address@hidden
- [Qemu-riscv] [PATCH v1 16/23] riscv: tcg-target: Add slowpath load and store instructions, (continued)
- [Qemu-riscv] [PATCH v1 16/23] riscv: tcg-target: Add slowpath load and store instructions, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 17/23] riscv: tcg-target: Add direct load and store instructions, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 18/23] riscv: tcg-target: Add the out op decoder, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 19/23] riscv: tcg-target: Add the prologue generation and register the JIT, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 20/23] riscv: tcg-target: Add the target init code, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 21/23] tcg: Add RISC-V cpu signal handler, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 22/23] dias: Add RISC-V support, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 23/23] configure: Add support for building RISC-V host, Alistair Francis, 2018/12/12
- Re: [Qemu-riscv] [PATCH v1 00/23] Add RISC-V TCG backend support, Richard Henderson, 2018/12/12
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 00/23] Add RISC-V TCG backend support,
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