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[Qemu-riscv] [PATCH v1 22/23] dias: Add RISC-V support
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From: |
Alistair Francis |
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Subject: |
[Qemu-riscv] [PATCH v1 22/23] dias: Add RISC-V support |
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Date: |
Wed, 12 Dec 2018 19:46:16 +0000 |
Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
disas.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/disas.c b/disas.c
index 5325b7e6be..e627fc74f9 100644
--- a/disas.c
+++ b/disas.c
@@ -522,8 +522,14 @@ void disas(FILE *out, void *code, unsigned long size)
# ifdef _ARCH_PPC64
s.info.cap_mode = CS_MODE_64;
# endif
-#elif defined(__riscv__)
- print_insn = print_insn_riscv;
+#elif defined(__riscv) && defined(CONFIG_RISCV_DIS)
+#if defined(_ILP32) || (__riscv_xlen == 32)
+ print_insn = print_insn_riscv32;
+#elif defined(_LP64)
+ print_insn = print_insn_riscv64;
+#else
+#error unsupported RISC-V ABI
+#endif
#elif defined(__aarch64__) && defined(CONFIG_ARM_A64_DIS)
print_insn = print_insn_arm_a64;
s.info.cap_arch = CS_ARCH_ARM64;
--
2.19.1
- [Qemu-riscv] [PATCH v1 12/23] riscv: tcg-target: Add the extract instructions, (continued)
- [Qemu-riscv] [PATCH v1 12/23] riscv: tcg-target: Add the extract instructions, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 13/23] riscv: tcg-target: Add the out load and store instructions, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 14/23] riscv: tcg-target: Add the add2 and sub2 instructions, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 15/23] riscv: tcg-target: Add branch and jump instructions, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 16/23] riscv: tcg-target: Add slowpath load and store instructions, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 17/23] riscv: tcg-target: Add direct load and store instructions, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 18/23] riscv: tcg-target: Add the out op decoder, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 19/23] riscv: tcg-target: Add the prologue generation and register the JIT, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 20/23] riscv: tcg-target: Add the target init code, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 21/23] tcg: Add RISC-V cpu signal handler, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 22/23] dias: Add RISC-V support,
Alistair Francis <=
- [Qemu-riscv] [PATCH v1 23/23] configure: Add support for building RISC-V host, Alistair Francis, 2018/12/12
- Re: [Qemu-riscv] [PATCH v1 00/23] Add RISC-V TCG backend support, Richard Henderson, 2018/12/12
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 00/23] Add RISC-V TCG backend support, no-reply, 2018/12/12