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[Qemu-riscv] [PULL 14/14] MAINTAINERS: Mark RISC-V as Supported
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From: |
Palmer Dabbelt |
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Subject: |
[Qemu-riscv] [PULL 14/14] MAINTAINERS: Mark RISC-V as Supported |
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Date: |
Fri, 21 Dec 2018 08:03:07 -0800 |
There's at least two of us that are paid to work on this.
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index d676c73f8840..317eff6cec4d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -262,7 +262,7 @@ M: Alistair Francis <address@hidden>
M: Sagar Karandikar <address@hidden>
M: Bastian Koppelmann <address@hidden>
L: address@hidden
-S: Maintained
+S: Supported
F: target/riscv/
F: hw/riscv/
F: include/hw/riscv/
--
2.18.1
- [Qemu-riscv] [PR RFC] RISC-V Changes for 3.2, Part 1, Palmer Dabbelt, 2018/12/21
- [Qemu-riscv] [PULL 01/14] hw/riscv/virt: Increase the number of interrupts, Palmer Dabbelt, 2018/12/21
- [Qemu-riscv] [PULL 02/14] hw/riscv/virt: Adjust memory layout spacing, Palmer Dabbelt, 2018/12/21
- [Qemu-riscv] [PULL 04/14] riscv: Enable VGA and PCIE_VGA, Palmer Dabbelt, 2018/12/21
- [Qemu-riscv] [PULL 03/14] hw/riscv/virt: Connect the gpex PCIe, Palmer Dabbelt, 2018/12/21
- [Qemu-riscv] [PULL 05/14] sifive_u: Add clock DT node for GEM ethernet, Palmer Dabbelt, 2018/12/21
- [Qemu-riscv] [PULL 06/14] sifive_u: Set 'clock-frequency' DT property for SiFive UART, Palmer Dabbelt, 2018/12/21
- [Qemu-riscv] [PULL 14/14] MAINTAINERS: Mark RISC-V as Supported,
Palmer Dabbelt <=
- [Qemu-riscv] [PULL 09/14] RISC-V: Fix PLIC pending bitfield reads, Palmer Dabbelt, 2018/12/21
- [Qemu-riscv] [PULL 11/14] sifive_uart: Implement interrupt pending register, Palmer Dabbelt, 2018/12/21
- [Qemu-riscv] [PULL 07/14] RISC-V: Add hartid and \n to interrupt logging, Palmer Dabbelt, 2018/12/21
- [Qemu-riscv] [PULL 10/14] RISC-V: Enable second UART on sifive_e and sifive_u, Palmer Dabbelt, 2018/12/21
- [Qemu-riscv] [PULL 08/14] RISC-V: Fix CLINT timecmp low 32-bit writes, Palmer Dabbelt, 2018/12/21
- [Qemu-riscv] [PULL 12/14] target/riscv/pmp.c: Fix pmp_decode_napot(), Palmer Dabbelt, 2018/12/21
- [Qemu-riscv] [PULL 13/14] riscv/cpu: use device_class_set_parent_realize, Palmer Dabbelt, 2018/12/21