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[Qemu-riscv] [PULL 12/14] target/riscv/pmp.c: Fix pmp_decode_napot()
From: |
Palmer Dabbelt |
Subject: |
[Qemu-riscv] [PULL 12/14] target/riscv/pmp.c: Fix pmp_decode_napot() |
Date: |
Fri, 21 Dec 2018 08:03:05 -0800 |
From: Anup Patel <address@hidden>
Currently, start and end address of a PMP region are not decoded
correctly by pmp_decode_napot().
Let's say we have a 128KB PMP region with base address as 0x80000000.
Now, the PMPADDRx CSR value for this region will be 0x20003fff.
The current pmp_decode_napot() implementation will decode PMPADDRx
CSR as t1=14, base=0x100000000, and range=0x1ffff whereas it should
have decoded PMPADDRx CSR as t1=14, base=0x80000000, and range=0x1fff.
This patch fixes the base value decoding in pmp_decode_napot() when
PMPADDRx CSR is not -1 (i.e. 0xffffffffffffffff).
Signed-off-by: Anup Patel <address@hidden>
Signed-off-by: Anup Patel <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
target/riscv/pmp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 03abd8fe5eb7..15a5366616bd 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -138,7 +138,7 @@ static void pmp_decode_napot(target_ulong a, target_ulong
*sa, target_ulong *ea)
return;
} else {
target_ulong t1 = ctz64(~a);
- target_ulong base = (a & ~(((target_ulong)1 << t1) - 1)) << 3;
+ target_ulong base = (a & ~(((target_ulong)1 << t1) - 1)) << 2;
target_ulong range = ((target_ulong)1 << (t1 + 3)) - 1;
*sa = base;
*ea = base + range;
--
2.18.1
- [Qemu-riscv] [PULL 04/14] riscv: Enable VGA and PCIE_VGA, (continued)
- [Qemu-riscv] [PULL 04/14] riscv: Enable VGA and PCIE_VGA, Palmer Dabbelt, 2018/12/21
- [Qemu-riscv] [PULL 03/14] hw/riscv/virt: Connect the gpex PCIe, Palmer Dabbelt, 2018/12/21
- [Qemu-riscv] [PULL 05/14] sifive_u: Add clock DT node for GEM ethernet, Palmer Dabbelt, 2018/12/21
- [Qemu-riscv] [PULL 06/14] sifive_u: Set 'clock-frequency' DT property for SiFive UART, Palmer Dabbelt, 2018/12/21
- [Qemu-riscv] [PULL 14/14] MAINTAINERS: Mark RISC-V as Supported, Palmer Dabbelt, 2018/12/21
- [Qemu-riscv] [PULL 09/14] RISC-V: Fix PLIC pending bitfield reads, Palmer Dabbelt, 2018/12/21
- [Qemu-riscv] [PULL 11/14] sifive_uart: Implement interrupt pending register, Palmer Dabbelt, 2018/12/21
- [Qemu-riscv] [PULL 07/14] RISC-V: Add hartid and \n to interrupt logging, Palmer Dabbelt, 2018/12/21
- [Qemu-riscv] [PULL 10/14] RISC-V: Enable second UART on sifive_e and sifive_u, Palmer Dabbelt, 2018/12/21
- [Qemu-riscv] [PULL 08/14] RISC-V: Fix CLINT timecmp low 32-bit writes, Palmer Dabbelt, 2018/12/21
- [Qemu-riscv] [PULL 12/14] target/riscv/pmp.c: Fix pmp_decode_napot(),
Palmer Dabbelt <=
- [Qemu-riscv] [PULL 13/14] riscv/cpu: use device_class_set_parent_realize, Palmer Dabbelt, 2018/12/21