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[Qemu-riscv] [RFC v1 15/23] riscv: plic: Always set sip.SEIP bit for HS
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From: |
Alistair Francis |
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Subject: |
[Qemu-riscv] [RFC v1 15/23] riscv: plic: Always set sip.SEIP bit for HS |
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Date: |
Fri, 24 May 2019 16:46:15 -0700 |
When the PLIC generates an interrupt ensure we always set it for the SIP
CSR that corresponds to the HS (V=0) register.
Signed-off-by: Alistair Francis <address@hidden>
---
hw/riscv/sifive_plic.c | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c
index 1e7e4c8d51..25da29fa3d 100644
--- a/hw/riscv/sifive_plic.c
+++ b/hw/riscv/sifive_plic.c
@@ -147,7 +147,17 @@ static void sifive_plic_update(SiFivePLICState *plic)
riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_MEIP,
BOOL_TO_MASK(level));
break;
case PLICMode_S:
- riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_SEIP,
BOOL_TO_MASK(level));
+ if (riscv_cpu_virt_enabled(env)) {
+ if (level) {
+ atomic_or(&env->bsip, MIP_SEIP);
+ g_assert(riscv_cpu_virt_enabled(env));
+ } else {
+ atomic_and(&env->bsip, ~MIP_SEIP);
+ g_assert(riscv_cpu_virt_enabled(env));
+ }
+ } else {
+ riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_SEIP,
BOOL_TO_MASK(level));
+ }
break;
default:
break;
--
2.21.0
- [Qemu-riscv] [RFC v1 00/23] Add RISC-V Hypervisor Extension, Alistair Francis, 2019/05/24
- Re: [Qemu-riscv] [RFC v1 00/23] Add RISC-V Hypervisor Extension, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 23/23] target/riscv: Allow enabling the Hypervisor extension, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 22/23] target/riscv: Call the second stage MMU in virtualisation mode, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 21/23] target/riscv: Implement second stage MMU, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 20/23] target/riscv: Allow specifying number of MMU stages, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 19/23] target/riscv: Allow specifying MMU stage, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 18/23] target/riscv: Add hfence instructions, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 17/23] target/riscv: Add Hypervisor trap return support, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 15/23] riscv: plic: Always set sip.SEIP bit for HS,
Alistair Francis <=
- [Qemu-riscv] [RFC v1 14/23] riscv: plic: Remove unused interrupt functions, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 13/23] target/riscv: Generate illegal instruction on WFI when V=1, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 16/23] target/riscv: Add hypvervisor trap support, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 10/23] target/riscv: Add background CSRs accesses, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 09/23] target/riscv: Add Hypervisor CSR access functions, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 08/23] target/riscv: Add support for background interrupt setting, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 04/23] target/riscv: Add the force HS exception mode, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 12/23] target/ricsv: Flush the TLB on virtulisation mode changes, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 11/23] target/riscv: Add background register swapping function, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 06/23] target/riscv: Dump Hypervisor registers if enabled, Alistair Francis, 2019/05/24