qemu-riscv (thread)

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qemu-riscv (thread)

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Last Modified: Fri May 31 2019 21:02:41 -0400
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[Qemu-riscv] Details about QEMU., sunny . desai, 2019/05/31
[Qemu-riscv] atomic failures on qemu-system-riscv64, Joel Sing, 2019/05/30
[Qemu-riscv] [PATCHv4 1/6] RISC-V: Only Check PMP if MMU translation succeeds, Hesham Almatary, 2019/05/30
- [Qemu-riscv] [PATCHv4 2/6] RISC-V: Raise access fault exceptions on PMP violations, Hesham Almatary, 2019/05/30
- [Qemu-riscv] [PATCHv4 3/6] RISC-V: Check for the effective memory privilege mode during PMP checks, Hesham Almatary, 2019/05/30
- [Qemu-riscv] [PATCHv4 4/6] RISC-V: Check PMP during Page Table Walks, Hesham Almatary, 2019/05/30
- [Qemu-riscv] [PATCHv4 5/6] RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off, Hesham Almatary, 2019/05/30
- [Qemu-riscv] [PATCHv4 6/6] RISC-V: Fix a PMP check with the correct access size, Hesham Almatary, 2019/05/30
[Qemu-riscv] [PATCH] sifive_prci: Read and write PRCI registers, Palmer Dabbelt, 2019/05/29
[Qemu-riscv] [PATCH] riscv: virt: Correct pci "bus-range" encoding, Bin Meng, 2019/05/29
- Re: [Qemu-riscv] [Qemu-devel] [PATCH] riscv: virt: Correct pci "bus-range" encoding, Alistair Francis, 2019/05/29
  - Re: [Qemu-riscv] [Qemu-devel] [PATCH] riscv: virt: Correct pci "bus-range" encoding, Bin Meng, 2019/05/29
[Qemu-riscv] [PATCH for 4.1 v3] target/riscv: Expose time CSRs when allowed by [m|s]counteren, Jonathan Behrens, 2019/05/28
Re: [Qemu-riscv] [PATCH for 4.1 v2] target/riscv: Expose time CSRs when allowed by [m|s]counteren, Palmer Dabbelt, 2019/05/28
- Re: [Qemu-riscv] [PATCH for 4.1 v2] target/riscv: Expose time CSRs when allowed by [m|s]counteren, Jonathan Behrens, 2019/05/28
[Qemu-riscv] [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 1, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 28/29] target/riscv: More accurate handling of `sip` CSR, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 29/29] target/riscv: Only flush TLB if SATP.ASID changes, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 27/29] target/riscv: Add checks for several RVC reserved operands, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 25/29] target/riscv: Add the HSTATUS register masks, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 26/29] target/riscv: Add the HGATP register masks, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 24/29] target/riscv: Add Hypervisor CSR macros, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 20/29] target/riscv: Trigger interrupt on MIP update asynchronously, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 23/29] target/riscv: Allow setting mstatus virtulisation bits, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 17/29] target/riscv: Deprecate the generic no MMU CPUs, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 16/29] target/riscv: Add a base 32 and 64 bit CPU, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 15/29] target/riscv: Create settable CPU properties, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 11/29] target/riscv: Remove spaces from register names, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 08/29] target/riscv: Use pattern groups in insn16.decode, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 19/29] target/riscv: Mark privilege level 2 as reserved, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 22/29] target/riscv: Add the MPV and MTL mstatus bits, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 21/29] target/riscv: Improve the scause logic, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 18/29] riscv: spike: Add a generic spike machine, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 13/29] linux-user/riscv: Add the CPU type as a comment, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 09/29] target/riscv: Split RVC32 and RVC64 insns into separate files, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 14/29] riscv: virt: Allow specifying a CPU via commandline, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 01/29] SiFive RISC-V GPIO Device, Palmer Dabbelt, 2019/05/25
  - Re: [Qemu-riscv] [PULL 01/29] SiFive RISC-V GPIO Device, Peter Maydell, 2019/05/30
- [Qemu-riscv] [PULL 12/29] target/riscv: Remove unused include of riscv_htif.h for virt board riscv, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 10/29] target/riscv: Split gen_arith_imm into functional and temp, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 07/29] target/riscv: Merge argument decode for RVC shifti, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 05/29] target/riscv: Use --static-decode for decodetree, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 06/29] target/riscv: Merge argument sets for insn32 and insn16, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 04/29] target/riscv: Name the argument sets for all of insn32 formats, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 03/29] RISC-V: fix single stepping over ret and other branching instructions, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 02/29] target/riscv: Do not allow sfence.vma from user mode, Palmer Dabbelt, 2019/05/25
- Re: [Qemu-riscv] [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 1, Peter Maydell, 2019/05/28
[Qemu-riscv] [RFC v1 00/23] Add RISC-V Hypervisor Extension, Alistair Francis, 2019/05/24
- Re: [Qemu-riscv] [RFC v1 00/23] Add RISC-V Hypervisor Extension, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 23/23] target/riscv: Allow enabling the Hypervisor extension, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 22/23] target/riscv: Call the second stage MMU in virtualisation mode, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 21/23] target/riscv: Implement second stage MMU, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 20/23] target/riscv: Allow specifying number of MMU stages, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 19/23] target/riscv: Allow specifying MMU stage, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 18/23] target/riscv: Add hfence instructions, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 17/23] target/riscv: Add Hypervisor trap return support, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 15/23] riscv: plic: Always set sip.SEIP bit for HS, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 14/23] riscv: plic: Remove unused interrupt functions, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 13/23] target/riscv: Generate illegal instruction on WFI when V=1, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 16/23] target/riscv: Add hypvervisor trap support, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 10/23] target/riscv: Add background CSRs accesses, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 09/23] target/riscv: Add Hypervisor CSR access functions, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 08/23] target/riscv: Add support for background interrupt setting, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 04/23] target/riscv: Add the force HS exception mode, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 12/23] target/ricsv: Flush the TLB on virtulisation mode changes, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 11/23] target/riscv: Add background register swapping function, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 06/23] target/riscv: Dump Hypervisor registers if enabled, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 01/23] target/riscv: Don't set write permissions on dirty PTEs, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 07/23] target/riscv: Remove strict perm checking for CSR R/W, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 03/23] target/riscv: Add the virtulisation mode, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 05/23] target/riscv: Add the Hypervisor CSRs to CPUState, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 02/23] target/riscv: Add the Hypervisor extension, Alistair Francis, 2019/05/24
[Qemu-riscv] [PATCHv3 4/5] RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off, Hesham Almatary, 2019/05/22
[Qemu-riscv] [PATCHv3 1/5] RISC-V: Only Check PMP if MMU translation succeeds, Hesham Almatary, 2019/05/21
- [Qemu-riscv] [PATCHv3 2/5] RISC-V: Raise access fault exceptions on PMP violations, Hesham Almatary, 2019/05/21
- [Qemu-riscv] [PATCHv3 3/5] RISC-V: Check PMP during Page Table Walks, Hesham Almatary, 2019/05/21
  - Re: [Qemu-riscv] [Qemu-devel] [PATCHv3 3/5] RISC-V: Check PMP during Page Table Walks, Alistair Francis, 2019/05/21
    - Re: [Qemu-riscv] [Qemu-devel] [PATCHv3 3/5] RISC-V: Check PMP during Page Table Walks, Hesham Almatary, 2019/05/22
    - Re: [Qemu-riscv] [Qemu-devel] [PATCHv3 3/5] RISC-V: Check PMP during Page Table Walks, Hesham Almatary, 2019/05/29
    - Re: [Qemu-riscv] [Qemu-devel] [PATCHv3 3/5] RISC-V: Check PMP during Page Table Walks, Alistair Francis, 2019/05/29
    - Re: [Qemu-riscv] [Qemu-devel] [PATCHv3 3/5] RISC-V: Check PMP during Page Table Walks, Hesham Almatary, 2019/05/30
- [Qemu-riscv] [PATCHv3 4/5] RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off, Hesham Almatary, 2019/05/21
  - Re: [Qemu-riscv] [Qemu-devel] [PATCHv3 4/5] RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off, Alistair Francis, 2019/05/21
- [Qemu-riscv] [PATCHv3 5/5] RISC-V: Fix a PMP check with the correct access size, Hesham Almatary, 2019/05/21
  - Re: [Qemu-riscv] [Qemu-devel] [PATCHv3 5/5] RISC-V: Fix a PMP check with the correct access size, Alistair Francis, 2019/05/21
    - Re: [Qemu-riscv] [Qemu-devel] [PATCHv3 5/5] RISC-V: Fix a PMP check with the correct access size, Jonathan Behrens, 2019/05/21
    - Re: [Qemu-riscv] [Qemu-devel] [PATCHv3 5/5] RISC-V: Fix a PMP check with the correct access size, Hesham Almatary, 2019/05/22
- Re: [Qemu-riscv] [Qemu-devel] [PATCHv3 1/5] RISC-V: Only Check PMP if MMU translation succeeds, Alistair Francis, 2019/05/21
- [Qemu-riscv] [PATCHv3 1/5] RISC-V: Only Check PMP if MMU translation succeeds, Hesham Almatary, 2019/05/22
  - Re: [Qemu-riscv] [Qemu-devel] [PATCHv3 1/5] RISC-V: Only Check PMP if MMU translation succeeds, Alistair Francis, 2019/05/29
[Qemu-riscv] [PATCHv2 1/3] RISC-V: Raise access fault exceptions on PMP violations, Hesham Almatary, 2019/05/18
- [Qemu-riscv] [PATCHv2 2/3] RISC-V: Only Check PMP if MMU translation succeeds, Hesham Almatary, 2019/05/18
  - Re: [Qemu-riscv] [Qemu-devel] [PATCHv2 2/3] RISC-V: Only Check PMP if MMU translation succeeds, Alistair Francis, 2019/05/20
- [Qemu-riscv] [PATCHv3 3/3] RISC-V: Check PMP during Page Table Walks, Hesham Almatary, 2019/05/18
- Re: [Qemu-riscv] [Qemu-devel] [PATCHv2 1/3] RISC-V: Raise access fault exceptions on PMP violations, Alistair Francis, 2019/05/20
[Qemu-riscv] [PATCH 1/2] RISC-V: Raise access fault exceptions on PMP violations, Hesham Almatary, 2019/05/18
- [Qemu-riscv] [PATCH 2/2] RISC-V: Only Check PMP if MMU translation succeeds, Hesham Almatary, 2019/05/18
- Re: [Qemu-riscv] [PATCH 1/2] RISC-V: Raise access fault exceptions on PMP violations, Jonathan Behrens, 2019/05/18
  - Re: [Qemu-riscv] [PATCH 1/2] RISC-V: Raise access fault exceptions on PMP violations, Hesham Almatary, 2019/05/18
[Qemu-riscv] [PATCH for-4.1 0/2] target/riscv: Improve virt machine kernel handling, Jonathan Behrens, 2019/05/17
- [Qemu-riscv] [PATCH for-4.1 1/2] target/riscv: virt machine shouldn't assume ELF entry is DRAM base, Jonathan Behrens, 2019/05/17
- [Qemu-riscv] [PATCH for-4.1 2/2] target/riscv: Add support for -bios "firmware_filename" flag, Jonathan Behrens, 2019/05/17
  - Re: [Qemu-riscv] [Qemu-devel] [PATCH for-4.1 2/2] target/riscv: Add support for -bios "firmware_filename" flag, Alistair Francis, 2019/05/17
    - Re: [Qemu-riscv] [Qemu-devel] [PATCH for-4.1 2/2] target/riscv: Add support for -bios "firmware_filename" flag, Jonathan Behrens, 2019/05/18
    - Re: [Qemu-riscv] [Qemu-devel] [PATCH for-4.1 2/2] target/riscv: Add support for -bios "firmware_filename" flag, Alistair Francis, 2019/05/20
    - Re: [Qemu-riscv] [Qemu-devel] [PATCH for-4.1 2/2] target/riscv: Add support for -bios "firmware_filename" flag, Jonathan Behrens, 2019/05/31
[Qemu-riscv] [PATCH v1 0/4] Miscellaneous patches from the RISC-V fork, Alistair Francis, 2019/05/17
- [Qemu-riscv] [PATCH v1 1/4] target/riscv: Fix PMP range boundary address bug, Alistair Francis, 2019/05/17
- [Qemu-riscv] [PATCH v1 3/4] disas/riscv: Fix `rdinstreth` constraint, Alistair Francis, 2019/05/17
- [Qemu-riscv] [PATCH v1 4/4] target/riscv: Implement riscv_cpu_unassigned_access, Alistair Francis, 2019/05/17
- [Qemu-riscv] [PATCH v1 2/4] disas/riscv: Disassemble reserved compressed encodings as illegal, Alistair Francis, 2019/05/17
Re: [Qemu-riscv] [PATCH 1/2] riscv: sifive_u: Do not create hard-coded phandles in DT, Alistair Francis, 2019/05/17
[Qemu-riscv] [PATCH 2/2] riscv: sifive_u: Update the plic hart config to support multicore, Bin Meng, 2019/05/17
- Re: [Qemu-riscv] [PATCH 2/2] riscv: sifive_u: Update the plic hart config to support multicore, Alistair Francis, 2019/05/17
[Qemu-riscv] Atomic issues on riscv64, Marco Peereboom, 2019/05/16
[Qemu-riscv] [PULL v2 17/27] target/riscv: Convert to CPUClass::tlb_fill, Richard Henderson, 2019/05/10
[Qemu-riscv] [PULL 17/27] target/riscv: Convert to CPUClass::tlb_fill, Richard Henderson, 2019/05/10
[Qemu-riscv] [PATCH v3 17/27] target/riscv: Convert to CPUClass::tlb_fill, Richard Henderson, 2019/05/09
[Qemu-riscv] [PATCH v2 17/27] target/riscv: Convert to CPUClass::tlb_fill, Richard Henderson, 2019/05/09
[Qemu-riscv] [PATCH] target/riscv: Only flush TLB if SATP.ASID changes, Jonathan Behrens, 2019/05/08
- Re: [Qemu-riscv] [Qemu-devel] [PATCH] target/riscv: Only flush TLB if SATP.ASID changes, Richard Henderson, 2019/05/08
- Re: [Qemu-riscv] [Qemu-devel] [PATCH] target/riscv: Only flush TLB if SATP.ASID changes, Alistair Francis, 2019/05/08
- Re: [Qemu-riscv] [PATCH] target/riscv: Only flush TLB if SATP.ASID changes, Palmer Dabbelt, 2019/05/08
[Qemu-riscv] [PATCH] target/riscv: More accurate handling of `sip` CSR, Jonathan Behrens, 2019/05/07
- Re: [Qemu-riscv] [PATCH] target/riscv: More accurate handling of `sip` CSR, Palmer Dabbelt, 2019/05/07
[Qemu-riscv] [PATCH v1 1/1] target/riscv: Allow setting ISA extensions via CPU props, Alistair Francis, 2019/05/06
- Re: [Qemu-riscv] [PATCH v1 1/1] target/riscv: Allow setting ISA extensions via CPU props, Palmer Dabbelt, 2019/05/28
[Qemu-riscv] [PATCH for 4.1] target/riscv: More accurate handling of `sip` CSR, Jonathan Behrens, 2019/05/06
- Re: [Qemu-riscv] [PATCH for 4.1] target/riscv: More accurate handling of `sip` CSR, Palmer Dabbelt, 2019/05/07
  - Re: [Qemu-riscv] [PATCH for 4.1] target/riscv: More accurate handling of `sip` CSR, Jonathan Behrens, 2019/05/07
[Qemu-riscv] [PATCH for 4.1] target/riscv: Only flush TLB if SATP.ASID changes, Jonathan Behrens, 2019/05/06
- Re: [Qemu-riscv] [PATCH for 4.1] target/riscv: Only flush TLB if SATP.ASID changes, Jonathan Behrens, 2019/05/06
[Qemu-riscv] RISC-V: qemu should provide different "model" strings in DT for RV64 and RV32, Karsten Merker, 2019/05/05
- Re: [Qemu-riscv] RISC-V: qemu should provide different "model" strings in DT for RV64 and RV32, Alistair Francis, 2019/05/06
  - Message not available
    - Re: [Qemu-riscv] RISC-V: qemu should provide different "model" strings in DT for RV64 and RV32, Alistair Francis, 2019/05/06
    - Re: [Qemu-riscv] RISC-V: qemu should provide different "model" strings in DT for RV64 and RV32, Palmer Dabbelt, 2019/05/07
Re: [Qemu-riscv] [Qemu-devel] [PATCH for-4.1 6/8] target/riscv: Split RVC32 and RVC64 insns into separate files, Alistair Francis, 2019/05/02

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