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qemu-riscv (date)
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Last Modified: Sat Jun 29 2019 15:44:35 -0400
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June 29, 2019
Re: [Qemu-riscv] [Qemu-devel] [PATCH] RISC-V: Fix pmpcfg register indexing
,
Luke Nelson
,
15:44
June 28, 2019
Re: [Qemu-riscv] [Qemu-devel] [PATCH] target/riscv: Hardwire mcounter.TM and upper bits of [m|s]counteren
,
Alistair Francis
,
18:02
Re: [Qemu-riscv] [Qemu-devel] [PATCH] target/riscv: Hardwire mcounter.TM and upper bits of [m|s]counteren
,
Jonathan Behrens
,
17:20
Re: [Qemu-riscv] [Qemu-devel] [PATCH] target/riscv: Hardwire mcounter.TM and upper bits of [m|s]counteren
,
Alistair Francis
,
17:04
Re: [Qemu-riscv] [Qemu-devel] [PATCH for 4.1 v3] target/riscv: Expose time CSRs when allowed by [m|s]counteren
,
Jonathan Behrens
,
16:15
[Qemu-riscv] [PATCH] target/riscv: Hardwire mcounter.TM and upper bits of [m|s]counteren
,
jonathan
,
16:12
Re: [Qemu-riscv] [Qemu-devel] [PATCH for 4.1 v3] target/riscv: Expose time CSRs when allowed by [m|s]counteren
,
Alistair Francis
,
14:26
[Qemu-riscv] [PULL 33/34] roms: Add OpenSBI version 0.3
,
Palmer Dabbelt
,
13:34
[Qemu-riscv] [PULL 34/34] hw/riscv: Load OpenSBI as the default firmware
,
Palmer Dabbelt
,
13:34
[Qemu-riscv] [PULL 31/34] hw/riscv: Add support for loading a firmware
,
Palmer Dabbelt
,
13:34
[Qemu-riscv] [PULL 30/34] hw/riscv: Split out the boot functions
,
Palmer Dabbelt
,
13:34
[Qemu-riscv] [PULL 32/34] hw/riscv: Extend the kernel loading support
,
Palmer Dabbelt
,
13:34
[Qemu-riscv] [PULL 29/34] riscv: sifive_u: Update the plic hart config to support multicore
,
Palmer Dabbelt
,
13:34
[Qemu-riscv] [PULL 27/34] disas/riscv: Fix `rdinstreth` constraint
,
Palmer Dabbelt
,
13:34
[Qemu-riscv] [PULL 28/34] riscv: sifive_u: Do not create hard-coded phandles in DT
,
Palmer Dabbelt
,
13:34
[Qemu-riscv] [PULL 25/34] riscv: virt: Add cpu-topology DT node.
,
Palmer Dabbelt
,
13:34
[Qemu-riscv] [PULL 23/34] RISC-V: Clear load reservations on context switch and SC
,
Palmer Dabbelt
,
13:34
[Qemu-riscv] [PULL 20/34] target/riscv: Add support for disabling/enabling Counters
,
Palmer Dabbelt
,
13:34
[Qemu-riscv] [PULL 26/34] disas/riscv: Disassemble reserved compressed encodings as illegal
,
Palmer Dabbelt
,
13:34
[Qemu-riscv] [PULL 24/34] RISC-V: Update syscall list for 32-bit support.
,
Palmer Dabbelt
,
13:34
[Qemu-riscv] [PULL 22/34] RISC-V: Add support for the Zicsr extension
,
Palmer Dabbelt
,
13:34
[Qemu-riscv] [PULL 16/34] target/riscv: Set privledge spec 1.11.0 as default
,
Palmer Dabbelt
,
13:34
[Qemu-riscv] [PULL 18/34] target/riscv: Require either I or E base extension
,
Palmer Dabbelt
,
13:34
[Qemu-riscv] [PULL 17/34] qemu-deprecated.texi: Deprecate the RISC-V privledge spec 1.09.1
,
Palmer Dabbelt
,
13:34
[Qemu-riscv] [PULL 09/34] RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off
,
Palmer Dabbelt
,
13:34
[Qemu-riscv] [PULL 08/34] RISC-V: Check PMP during Page Table Walks
,
Palmer Dabbelt
,
13:34
[Qemu-riscv] [PULL 19/34] target/riscv: Remove user version information
,
Palmer Dabbelt
,
13:34
[Qemu-riscv] [PULL 21/34] RISC-V: Add support for the Zifencei extension
,
Palmer Dabbelt
,
13:34
[Qemu-riscv] [PULL 13/34] target/riscv: Restructure deprecatd CPUs
,
Palmer Dabbelt
,
13:34
[Qemu-riscv] [PULL 15/34] target/riscv: Add the mcountinhibit CSR
,
Palmer Dabbelt
,
13:33
[Qemu-riscv] [PULL 11/34] riscv: virt: Correct pci "bus-range" encoding
,
Palmer Dabbelt
,
13:33
[Qemu-riscv] [PULL 14/34] target/riscv: Add the privledge spec version 1.11.0
,
Palmer Dabbelt
,
13:33
[Qemu-riscv] [PULL 12/34] RISC-V: Fix a memory leak when realizing a sifive_e
,
Palmer Dabbelt
,
13:33
[Qemu-riscv] [PULL 07/34] RISC-V: Check for the effective memory privilege mode during PMP checks
,
Palmer Dabbelt
,
13:33
[Qemu-riscv] [PULL 06/34] RISC-V: Raise access fault exceptions on PMP violations
,
Palmer Dabbelt
,
13:33
[Qemu-riscv] [PULL 10/34] RISC-V: Fix a PMP check with the correct access size
,
Palmer Dabbelt
,
13:33
[Qemu-riscv] [PULL 04/34] target/riscv: Implement riscv_cpu_unassigned_access
,
Palmer Dabbelt
,
13:33
[Qemu-riscv] [PULL 05/34] RISC-V: Only Check PMP if MMU translation succeeds
,
Palmer Dabbelt
,
13:33
[Qemu-riscv] [PULL 03/34] target/riscv: Fix PMP range boundary address bug
,
Palmer Dabbelt
,
13:33
[Qemu-riscv] [PULL 02/34] sifive_prci: Read and write PRCI registers
,
Palmer Dabbelt
,
13:33
[Qemu-riscv] [PULL 01/34] target/riscv: Allow setting ISA extensions via CPU props
,
Palmer Dabbelt
,
13:32
[Qemu-riscv] [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v2
,
Palmer Dabbelt
,
13:32
Re: [Qemu-riscv] [PATCH] fixup! roms: Add OpenSBI version 0.3
,
Palmer Dabbelt
,
13:18
Re: [Qemu-riscv] [Qemu-devel] [PULL 33/34] roms: Add OpenSBI version 0.3
,
Palmer Dabbelt
,
13:11
[Qemu-riscv] [PATCH] fixup! roms: Add OpenSBI version 0.3
,
Alistair Francis
,
12:18
Re: [Qemu-riscv] [Qemu-devel] [PULL 33/34] roms: Add OpenSBI version 0.3
,
Alistair Francis
,
12:16
Re: [Qemu-riscv] [Qemu-devel] [PULL 33/34] roms: Add OpenSBI version 0.3
,
Jonathan Cameron
,
05:46
Re: [Qemu-riscv] [Qemu-devel] [PATCH for 4.1 v3] target/riscv: Expose time CSRs when allowed by [m|s]counteren
,
Palmer Dabbelt
,
02:12
June 27, 2019
Re: [Qemu-riscv] [Qemu-devel] [PATCH for 4.1 v3] target/riscv: Expose time CSRs when allowed by [m|s]counteren
,
Alistair Francis
,
16:00
Re: [Qemu-riscv] [Qemu-devel] [PULL 10/34] RISC-V: Fix a PMP check with the correct access size
,
Richard Henderson
,
14:23
Re: [Qemu-riscv] [PULL 10/34] RISC-V: Fix a PMP check with the correct access size
,
Jonathan Behrens
,
13:44
Re: [Qemu-riscv] [Qemu-devel] [PATCHv4 3/6] RISC-V: Check for the effective memory privilege mode during PMP checks
,
Richard Henderson
,
13:01
[Qemu-riscv] [PULL 25/34] riscv: virt: Add cpu-topology DT node.
,
Palmer Dabbelt
,
11:26
[Qemu-riscv] [PULL 30/34] hw/riscv: Split out the boot functions
,
Palmer Dabbelt
,
11:26
[Qemu-riscv] [PULL 24/34] RISC-V: Update syscall list for 32-bit support.
,
Palmer Dabbelt
,
11:26
[Qemu-riscv] [PULL 16/34] target/riscv: Set privledge spec 1.11.0 as default
,
Palmer Dabbelt
,
11:26
[Qemu-riscv] [PULL 32/34] hw/riscv: Extend the kernel loading support
,
Palmer Dabbelt
,
11:26
[Qemu-riscv] [PULL 28/34] riscv: sifive_u: Do not create hard-coded phandles in DT
,
Palmer Dabbelt
,
11:26
[Qemu-riscv] [PULL 33/34] roms: Add OpenSBI version 0.3
,
Palmer Dabbelt
,
11:26
[Qemu-riscv] [PULL 09/34] RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off
,
Palmer Dabbelt
,
11:26
[Qemu-riscv] [PULL 11/34] riscv: virt: Correct pci "bus-range" encoding
,
Palmer Dabbelt
,
11:26
[Qemu-riscv] [PULL 23/34] RISC-V: Clear load reservations on context switch and SC
,
Palmer Dabbelt
,
11:26
[Qemu-riscv] [PULL 26/34] disas/riscv: Disassemble reserved compressed encodings as illegal
,
Palmer Dabbelt
,
11:26
[Qemu-riscv] [PULL 34/34] hw/riscv: Load OpenSBI as the default firmware
,
Palmer Dabbelt
,
11:26
[Qemu-riscv] [PULL 17/34] qemu-deprecated.texi: Deprecate the RISC-V privledge spec 1.09.1
,
Palmer Dabbelt
,
11:26
[Qemu-riscv] [PULL 14/34] target/riscv: Add the privledge spec version 1.11.0
,
Palmer Dabbelt
,
11:26
[Qemu-riscv] [PULL 18/34] target/riscv: Require either I or E base extension
,
Palmer Dabbelt
,
11:26
[Qemu-riscv] [PULL 06/34] RISC-V: Raise access fault exceptions on PMP violations
,
Palmer Dabbelt
,
11:26
[Qemu-riscv] [PULL 29/34] riscv: sifive_u: Update the plic hart config to support multicore
,
Palmer Dabbelt
,
11:26
[Qemu-riscv] [PULL 12/34] RISC-V: Fix a memory leak when realizing a sifive_e
,
Palmer Dabbelt
,
11:26
[Qemu-riscv] [PULL 15/34] target/riscv: Add the mcountinhibit CSR
,
Palmer Dabbelt
,
11:26
[Qemu-riscv] [PULL 22/34] RISC-V: Add support for the Zicsr extension
,
Palmer Dabbelt
,
11:25
[Qemu-riscv] [PULL 20/34] target/riscv: Add support for disabling/enabling Counters
,
Palmer Dabbelt
,
11:25
[Qemu-riscv] [PULL 07/34] RISC-V: Check for the effective memory privilege mode during PMP checks
,
Palmer Dabbelt
,
11:25
[Qemu-riscv] [PULL 13/34] target/riscv: Restructure deprecatd CPUs
,
Palmer Dabbelt
,
11:25
[Qemu-riscv] [PULL 31/34] hw/riscv: Add support for loading a firmware
,
Palmer Dabbelt
,
11:25
[Qemu-riscv] [PULL 21/34] RISC-V: Add support for the Zifencei extension
,
Palmer Dabbelt
,
11:25
[Qemu-riscv] [PULL 08/34] RISC-V: Check PMP during Page Table Walks
,
Palmer Dabbelt
,
11:25
[Qemu-riscv] [PULL 27/34] disas/riscv: Fix `rdinstreth` constraint
,
Palmer Dabbelt
,
11:25
[Qemu-riscv] [PULL 10/34] RISC-V: Fix a PMP check with the correct access size
,
Palmer Dabbelt
,
11:25
[Qemu-riscv] [PULL 19/34] target/riscv: Remove user version information
,
Palmer Dabbelt
,
11:24
[Qemu-riscv] [PULL 04/34] target/riscv: Implement riscv_cpu_unassigned_access
,
Palmer Dabbelt
,
11:24
[Qemu-riscv] [PULL 03/34] target/riscv: Fix PMP range boundary address bug
,
Palmer Dabbelt
,
11:24
[Qemu-riscv] [PULL 05/34] RISC-V: Only Check PMP if MMU translation succeeds
,
Palmer Dabbelt
,
11:24
[Qemu-riscv] [PULL 02/34] sifive_prci: Read and write PRCI registers
,
Palmer Dabbelt
,
11:23
[Qemu-riscv] [PULL 01/34] target/riscv: Allow setting ISA extensions via CPU props
,
Palmer Dabbelt
,
11:23
[Qemu-riscv] [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2
,
Palmer Dabbelt
,
11:23
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 0/5] RISC-V: Add firmware loading support and default
,
Andrea Bolognani
,
09:49
[Qemu-riscv] [PATCHv4 5/6] RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off
,
Hesham Almatary
,
08:19
[Qemu-riscv] [PATCHv4 4/6] RISC-V: Check PMP during Page Table Walks
,
Hesham Almatary
,
08:19
[Qemu-riscv] [PATCHv4 6/6] RISC-V: Fix a PMP check with the correct access size
,
Hesham Almatary
,
08:19
[Qemu-riscv] [PATCHv4 1/6] RISC-V: Only Check PMP if MMU translation succeeds
,
Hesham Almatary
,
08:19
[Qemu-riscv] [PATCHv4 3/6] RISC-V: Check for the effective memory privilege mode during PMP checks
,
Hesham Almatary
,
08:19
[Qemu-riscv] [PATCHv4 2/6] RISC-V: Raise access fault exceptions on PMP violations
,
Hesham Almatary
,
08:19
Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 4/5] roms: Add OpenSBI version 0.3
,
Jonathan Cameron
,
07:45
June 26, 2019
Re: [Qemu-riscv] [Qemu-devel] [PATCH] atomic failures on qemu-system-riscv64
,
Palmer Dabbelt
,
04:32
Re: [Qemu-riscv] [Qemu-devel] [PATCH] atomic failures on qemu-system-riscv64
,
Richard Henderson
,
04:30
Re: [Qemu-riscv] [Qemu-devel] [PATCH] atomic failures on qemu-system-riscv64
,
Palmer Dabbelt
,
04:25
Re: [Qemu-riscv] [Qemu-devel] [PATCH for 4.1 v3] target/riscv: Expose time CSRs when allowed by [m|s]counteren
,
Palmer Dabbelt
,
04:25
Re: [Qemu-riscv] [Qemu-devel] [PATCH for 4.1 v3] target/riscv: Expose time CSRs when allowed by [m|s]counteren
,
Palmer Dabbelt
,
04:25
Re: [Qemu-riscv] [Qemu-devel] [PATCH] riscv: virt: Correct pci "bus-range" encoding
,
Palmer Dabbelt
,
04:02
Re: [Qemu-riscv] [PATCH 2/2] riscv: sifive_u: Update the plic hart config to support multicore
,
Palmer Dabbelt
,
03:59
Re: [Qemu-riscv] [PATCH 1/2] riscv: sifive_u: Do not create hard-coded phandles in DT
,
Palmer Dabbelt
,
03:59
Re: [Qemu-riscv] [Qemu-devel] [PATCH] atomic failures on qemu-system-riscv64
,
Richard Henderson
,
03:48
Re: [Qemu-riscv] [Qemu-devel] [PATCH for 4.1 v3] target/riscv: Expose time CSRs when allowed by [m|s]counteren
,
Bin Meng
,
02:58
Re: [Qemu-riscv] [Qemu-devel] [PATCH for 4.1 v3] target/riscv: Expose time CSRs when allowed by [m|s]counteren
,
Bin Meng
,
02:54
Re: [Qemu-riscv] [PATCH v1 0/5] RISC-V: Add firmware loading support and default
,
Palmer Dabbelt
,
02:21
Re: [Qemu-riscv] [Qemu-devel] [PATCH] atomic failures on qemu-system-riscv64
,
Palmer Dabbelt
,
02:07
Re: [Qemu-riscv] [Qemu-devel] [PATCH] atomic failures on qemu-system-riscv64
,
Palmer Dabbelt
,
02:07
Re: [Qemu-riscv] [Qemu-devel] [PATCH] RISC-V: Add support for the Zicsr extension
,
Palmer Dabbelt
,
02:07
June 25, 2019
Re: [Qemu-riscv] [Qemu-devel] [PATCH] riscv: virt: Correct pci "bus-range" encoding
,
Bin Meng
,
21:47
Re: [Qemu-riscv] [PATCH 1/2] riscv: sifive_u: Do not create hard-coded phandles in DT
,
Bin Meng
,
21:47
Re: [Qemu-riscv] [Qemu-devel] [PATCH] riscv: sifive_test: Add reset functionality
,
Bin Meng
,
21:46
Re: [Qemu-riscv] [PATCH for 4.1 v3] target/riscv: Expose time CSRs when allowed by [m|s]counteren
,
Jonathan Behrens
,
16:23
Re: [Qemu-riscv] [PATCH v1 0/5] RISC-V: Add firmware loading support and default
,
Alistair Francis
,
13:09
Re: [Qemu-riscv] [Qemu-devel] [PATCH] atomic failures on qemu-system-riscv64
,
Richard Henderson
,
11:39
Re: [Qemu-riscv] [Qemu-devel] [PATCH] atomic failures on qemu-system-riscv64
,
Richard Henderson
,
11:36
Re: [Qemu-riscv] [Qemu-devel] [PATCH] RISC-V: Add support for the Zicsr extension
,
Alistair Francis
,
11:21
Re: [Qemu-riscv] [PATCH v1 1/1] tcg/riscv: Fix RISC-VH host build failure
,
Richard Henderson
,
10:38
Re: [Qemu-riscv] [Qemu-devel] [PATCH] riscv: virt: Add cpu-topology DT node.
,
Philippe Mathieu-Daudé
,
07:27
Re: [Qemu-riscv] [Qemu-devel] [PATCH] riscv: virt: Add cpu-topology DT node.
,
Daniel P . Berrangé
,
06:42
Re: [Qemu-riscv] [Qemu-devel] [PATCH] riscv: virt: Add cpu-topology DT node.
,
Philippe Mathieu-Daudé
,
06:36
Re: [Qemu-riscv] [PATCH v2 0/4] Miscellaneous patches from the RISC-V fork
,
Palmer Dabbelt
,
06:20
Re: [Qemu-riscv] [Qemu-devel] [PATCH v2] riscv: virt: Add cpu-topology DT node.
,
Palmer Dabbelt
,
06:20
[Qemu-riscv] [PATCH] RISC-V: Add support for the Zicsr extension
,
Palmer Dabbelt
,
06:08
Re: [Qemu-riscv] [PATCH v1 9/9] target/riscv: Add Zifencei and Zicsr as command line options
,
Palmer Dabbelt
,
06:08
[Qemu-riscv] [PATCH] RISC-V: Add support for the Zifencei extension
,
Palmer Dabbelt
,
06:08
Re: [Qemu-riscv] [PATCH for 4.1 v3] target/riscv: Expose time CSRs when allowed by [m|s]counteren
,
Palmer Dabbelt
,
05:56
Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 5/5] hw/riscv: Load OpenSBI as the default firmware
,
Bin Meng
,
05:20
Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 4/5] roms: Add OpenSBI version 0.3
,
Bin Meng
,
05:20
Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 2/5] hw/riscv: Add support for loading a firmware
,
Bin Meng
,
05:20
Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 3/5] hw/riscv: Extend the kernel loading support
,
Bin Meng
,
05:20
June 24, 2019
Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 0/4] Miscellaneous patches from the RISC-V fork
,
no-reply
,
21:15
[Qemu-riscv] [PATCH v2 4/4] target/riscv: Implement riscv_cpu_unassigned_access
,
Alistair Francis
,
19:45
[Qemu-riscv] [PATCH v2 3/4] disas/riscv: Fix `rdinstreth` constraint
,
Alistair Francis
,
19:45
[Qemu-riscv] [PATCH v2 1/4] target/riscv: Fix PMP range boundary address bug
,
Alistair Francis
,
19:45
[Qemu-riscv] [PATCH v2 2/4] disas/riscv: Disassemble reserved compressed encodings as illegal
,
Alistair Francis
,
19:45
[Qemu-riscv] [PATCH v2 0/4] Miscellaneous patches from the RISC-V fork
,
Alistair Francis
,
19:45
Re: [Qemu-riscv] [Qemu-devel] [PATCH] riscv: virt: Add cpu-topology DT node.
,
Atish Patra
,
19:42
[Qemu-riscv] [Qemu-devel] [PATCH v2] riscv: virt: Add cpu-topology DT node.
,
Atish Patra
,
19:42
Re: [Qemu-riscv] [Qemu-devel] [PATCH] riscv: virt: Add cpu-topology DT node.
,
Alistair Francis
,
19:27
Re: [Qemu-riscv] [PATCH v1 9/9] target/riscv: Add Zifencei and Zicsr as command line options
,
Alistair Francis
,
19:19
Re: [Qemu-riscv] [PATCH for 4.1 v3] target/riscv: Expose time CSRs when allowed by [m|s]counteren
,
Jonathan Behrens
,
19:04
[Qemu-riscv] [Qemu-devel] [PATCH] riscv: virt: Add cpu-topology DT node.
,
Atish Patra
,
18:57
[Qemu-riscv] [PATCH v1 4/5] roms: Add OpenSBI version 0.3
,
Alistair Francis
,
18:15
[Qemu-riscv] [PATCH v1 5/5] hw/riscv: Load OpenSBI as the default firmware
,
Alistair Francis
,
18:14
[Qemu-riscv] [PATCH v1 2/5] hw/riscv: Add support for loading a firmware
,
Alistair Francis
,
18:14
[Qemu-riscv] [PATCH v1 3/5] hw/riscv: Extend the kernel loading support
,
Alistair Francis
,
18:14
[Qemu-riscv] [PATCH v1 0/5] RISC-V: Add firmware loading support and default
,
Alistair Francis
,
18:14
[Qemu-riscv] [PATCH v1 1/5] hw/riscv: Split out the boot functions
,
Alistair Francis
,
18:14
Re: [Qemu-riscv] [PATCH v1 3/9] target/riscv: Comment in the mcountinhibit CSR
,
Alistair Francis
,
16:18
Re: [Qemu-riscv] [PATCH v1 0/9] Update the RISC-V specification versions
,
Alistair Francis
,
16:16
Re: [Qemu-riscv] [Qemu-devel] [PATCH] atomic failures on qemu-system-riscv64
,
Joel Sing
,
14:09
Re: [Qemu-riscv] [PATCH v1 0/9] Update the RISC-V specification versions
,
Palmer Dabbelt
,
05:33
Re: [Qemu-riscv] [PATCH v1 3/9] target/riscv: Comment in the mcountinhibit CSR
,
Palmer Dabbelt
,
05:32
Re: [Qemu-riscv] [PATCH v1 9/9] target/riscv: Add Zifencei and Zicsr as command line options
,
Palmer Dabbelt
,
05:32
Re: [Qemu-riscv] [Qemu-devel] [PATCH] atomic failures on qemu-system-riscv64
,
Palmer Dabbelt
,
02:43
June 23, 2019
Re: [Qemu-riscv] [PATCH v1 0/9] Update the RISC-V specification versions
,
Palmer Dabbelt
,
10:40
Re: [Qemu-riscv] [Qemu-devel] [PATCH] riscv: sifive_test: Add reset functionality
,
Palmer Dabbelt
,
10:40
June 21, 2019
Re: [Qemu-riscv] [PATCH v1 0/9] Update the RISC-V specification versions
,
Alistair Francis
,
20:26
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 4/5] roms: Add OpenSBI version 0.3
,
Alistair Francis
,
18:44
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 0/5] RISC-V: Add firmware loading support and default
,
Andrea Bolognani
,
08:36
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 4/5] roms: Add OpenSBI version 0.3
,
Bin Meng
,
01:42
Re: [Qemu-riscv] [Qemu-devel] [PATCH] riscv: sifive_test: Add reset functionality
,
Bin Meng
,
01:40
June 20, 2019
Re: [Qemu-riscv] [Qemu-devel] [PATCH] riscv: sifive_test: Add reset functionality
,
Palmer Dabbelt
,
22:53
Re: [Qemu-riscv] [PATCH v1 0/9] Update the RISC-V specification versions
,
Palmer Dabbelt
,
22:49
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 0/5] RISC-V: Add firmware loading support and default
,
David Abdurachmanov
,
14:44
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 0/5] RISC-V: Add firmware loading support and default
,
Alistair Francis
,
14:17
[Qemu-riscv] [PATCH v1 1/1] tcg/riscv: Fix RISC-VH host build failure
,
Alistair Francis
,
10:12
Re: [Qemu-riscv] TLB refresh issue
,
Quentin Mundell
,
07:18
Re: [Qemu-riscv] TLB refresh issue
,
Quentin Mundell
,
06:18
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 0/5] RISC-V: Add firmware loading support and default
,
Andrea Bolognani
,
04:17
June 19, 2019
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 3/5] hw/riscv: Extend the kernel loading support
,
Alistair Francis
,
18:09
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 3/5] hw/riscv: Extend the kernel loading support
,
Alistair Francis
,
17:05
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 2/5] hw/riscv: Add support for loading a firmware
,
Alistair Francis
,
17:03
Re: [Qemu-riscv] [PATCH v1 2/4] disas/riscv: Disassemble reserved compressed encodings as illegal
,
Alistair Francis
,
16:29
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 1/5] hw/riscv: Split out the boot functions
,
Alistair Francis
,
14:32
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 4/5] roms: Add OpenSBI version 0.3
,
Alistair Francis
,
14:32
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 0/5] RISC-V: Add firmware loading support and default
,
Alistair Francis
,
14:26
Re: [Qemu-riscv] TLB refresh issue
,
Jonathan Behrens
,
13:44
[Qemu-riscv] TLB refresh issue
,
Quentin Mundell
,
11:33
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 2/5] hw/riscv: Add support for loading a firmware
,
Bin Meng
,
11:30
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 2/5] hw/riscv: Add support for loading a firmware
,
Jonathan Behrens
,
11:26
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 4/5] roms: Add OpenSBI version 0.3
,
Bin Meng
,
11:18
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 3/5] hw/riscv: Extend the kernel loading support
,
Bin Meng
,
11:16
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 2/5] hw/riscv: Add support for loading a firmware
,
Bin Meng
,
11:16
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 1/5] hw/riscv: Split out the boot functions
,
Bin Meng
,
11:16
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 0/5] RISC-V: Add firmware loading support and default
,
Bin Meng
,
10:56
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 0/5] RISC-V: Add firmware loading support and default
,
Alistair Francis
,
10:30
Re: [Qemu-riscv] [Qemu-devel] RISC-V: Include ROM in QEMU
,
Alistair Francis
,
10:28
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 0/5] RISC-V: Add firmware loading support and default
,
Bin Meng
,
10:26
Re: [Qemu-riscv] [PATCH v1 0/9] Update the RISC-V specification versions
,
Alistair Francis
,
10:20
Re: [Qemu-riscv] [Qemu-devel] [PATCH] riscv: sifive_test: Add reset functionality
,
Bin Meng
,
09:42
Re: [Qemu-riscv] [PATCH v1 0/9] Update the RISC-V specification versions
,
Palmer Dabbelt
,
06:58
Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 33/50] target/riscv: fetch code with translator_ld
,
Palmer Dabbelt
,
06:49
Re: [Qemu-riscv] [RFC v1 5/5] hw/riscv: Load OpenSBI as the default firmware
,
Anup Patel
,
01:16
Re: [Qemu-riscv] [RFC v1 4/5] roms: Add OpenSBI version 0.3
,
Anup Patel
,
01:14
June 18, 2019
[Qemu-riscv] [RFC v1 4/5] roms: Add OpenSBI version 0.3
,
Alistair Francis
,
20:51
[Qemu-riscv] [RFC v1 0/5] RISC-V: Add firmware loading support and default
,
Alistair Francis
,
20:51
[Qemu-riscv] [RFC v1 1/5] hw/riscv: Split out the boot functions
,
Alistair Francis
,
20:51
[Qemu-riscv] [RFC v1 2/5] hw/riscv: Add support for loading a firmware
,
Alistair Francis
,
20:51
[Qemu-riscv] [RFC v1 3/5] hw/riscv: Extend the kernel loading support
,
Alistair Francis
,
20:51
[Qemu-riscv] [RFC v1 5/5] hw/riscv: Load OpenSBI as the default firmware
,
Alistair Francis
,
20:51
Re: [Qemu-riscv] [Qemu-devel] RISC-V: Include ROM in QEMU
,
Alistair Francis
,
18:20
Re: [Qemu-riscv] RISC-V: Include ROM in QEMU
,
Alistair Francis
,
18:20
Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 1/9] target/riscv: Restructure deprecatd CPUs
,
Alistair Francis
,
12:03
Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 1/9] target/riscv: Restructure deprecatd CPUs
,
Philippe Mathieu-Daudé
,
01:23
June 17, 2019
[Qemu-riscv] [PATCH v1 9/9] target/riscv: Add Zifencei and Zicsr as command line options
,
Alistair Francis
,
21:34
[Qemu-riscv] [PATCH v1 8/9] target/riscv: Add support for disabling/enabling Counters
,
Alistair Francis
,
21:34
[Qemu-riscv] [PATCH v1 7/9] target/riscv: Remove user version information
,
Alistair Francis
,
21:34
[Qemu-riscv] [PATCH v1 6/9] target/riscv: Require either I or E base extension
,
Alistair Francis
,
21:34
[Qemu-riscv] [PATCH v1 5/9] qemu-deprecated.texi: Deprecate the RISC-V privledge spec 1.09.1
,
Alistair Francis
,
21:33
[Qemu-riscv] [PATCH v1 4/9] target/riscv: Set privledge spec 1.11.0 as default
,
Alistair Francis
,
21:33
[Qemu-riscv] [PATCH v1 1/9] target/riscv: Restructure deprecatd CPUs
,
Alistair Francis
,
21:33
[Qemu-riscv] [PATCH v1 0/9] Update the RISC-V specification versions
,
Alistair Francis
,
21:33
[Qemu-riscv] [PATCH v1 3/9] target/riscv: Comment in the mcountinhibit CSR
,
Alistair Francis
,
21:33
[Qemu-riscv] [PATCH v1 2/9] target/riscv: Add the privledge spec version 1.11.0
,
Alistair Francis
,
21:33
Re: [Qemu-riscv] [Qemu-devel] [PATCH] atomic failures on qemu-system-riscv64
,
Richard Henderson
,
19:53
Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 33/50] target/riscv: fetch code with translator_ld
,
Richard Henderson
,
18:39
Re: [Qemu-riscv] [Qemu-devel] [PATCH] RISC-V: Fix a memory leak when realizing a sifive_e
,
Alistair Francis
,
13:21
Re: [Qemu-riscv] [Qemu-devel] [PATCH] riscv: sifive_test: Add reset functionality
,
Alistair Francis
,
13:15
Re: [Qemu-riscv] [PATCH v1 3/4] disas/riscv: Fix `rdinstreth` constraint
,
Alistair Francis
,
13:08
Re: [Qemu-riscv] [PULL 01/29] SiFive RISC-V GPIO Device
,
Fabien Chouteau
,
04:47
June 16, 2019
Re: [Qemu-riscv] [Qemu-devel] [PATCH] atomic failures on qemu-system-riscv64
,
no-reply
,
17:02
[Qemu-riscv] [PATCH] atomic failures on qemu-system-riscv64
,
Joel Sing
,
15:20
Re: [Qemu-riscv] [Qemu-devel] [PATCH] RISC-V: Fix a memory leak when realizing a sifive_e
,
Palmer Dabbelt
,
04:15
June 14, 2019
[Qemu-riscv] [PATCH v3 33/50] target/riscv: fetch code with translator_ld
,
Alex Bennée
,
13:19
[Qemu-riscv] [PATCH] riscv: sifive_test: Add reset functionality
,
Bin Meng
,
11:16
Re: [Qemu-riscv] [Qemu-devel] [PATCH] RISC-V: Fix a memory leak when realizing a sifive_e
,
Philippe Mathieu-Daudé
,
08:26
[Qemu-riscv] [PATCH] RISC-V: Fix a memory leak when realizing a sifive_e
,
Palmer Dabbelt
,
08:10
Re: [Qemu-riscv] [PULL 01/29] SiFive RISC-V GPIO Device
,
Palmer Dabbelt
,
08:10
Re: [Qemu-riscv] [PATCH for 4.1 v3] target/riscv: Expose time CSRs when allowed by [m|s]counteren
,
Palmer Dabbelt
,
07:52
Re: [Qemu-riscv] [PATCH v1 0/4] Miscellaneous patches from the RISC-V fork
,
Palmer Dabbelt
,
05:46
Re: [Qemu-riscv] [PATCH v1 4/4] target/riscv: Implement riscv_cpu_unassigned_access
,
Palmer Dabbelt
,
05:41
Re: [Qemu-riscv] [PATCH v1 3/4] disas/riscv: Fix `rdinstreth` constraint
,
Palmer Dabbelt
,
05:41
Re: [Qemu-riscv] [PATCH v1 2/4] disas/riscv: Disassemble reserved compressed encodings as illegal
,
Palmer Dabbelt
,
05:19
June 11, 2019
Re: [Qemu-riscv] [Qemu-devel] RISC-V: Include ROM in QEMU
,
Gerd Hoffmann
,
09:10
June 08, 2019
Re: [Qemu-riscv] [Qemu-devel] Fwd: [address@hidden: atomic failures on qemu-system-riscv64]
,
Palmer Dabbelt
,
01:41
June 07, 2019
Re: [Qemu-riscv] RISC-V: Include ROM in QEMU
,
Palmer Dabbelt
,
20:18
[Qemu-riscv] [PATCH v1 26/27] target/riscv: Call the second stage MMU in virtualisation mode
,
Alistair Francis
,
17:59
[Qemu-riscv] [PATCH v1 27/27] target/riscv: Allow enabling the Hypervisor extension
,
Alistair Francis
,
17:59
[Qemu-riscv] [PATCH v1 20/27] target/riscv: Disable guest FP support based on backgrond status
,
Alistair Francis
,
17:59
[Qemu-riscv] [PATCH v1 24/27] target/riscv: Allow specifying number of MMU stages
,
Alistair Francis
,
17:59
[Qemu-riscv] [PATCH v1 25/27] target/riscv: Implement second stage MMU
,
Alistair Francis
,
17:59
[Qemu-riscv] [PATCH v1 23/27] target/riscv: Allow specifying MMU stage
,
Alistair Francis
,
17:59
[Qemu-riscv] [PATCH v1 21/27] target/riscv: Mark both sstatus and bsstatus as dirty
,
Alistair Francis
,
17:59
[Qemu-riscv] [PATCH v1 22/27] target/riscv: Respect MPRV and SPRV for floating point ops
,
Alistair Francis
,
17:59
[Qemu-riscv] [PATCH v1 19/27] target/riscv: Add hfence instructions
,
Alistair Francis
,
17:59
[Qemu-riscv] [PATCH v1 14/27] target/riscv: Generate illegal instruction on WFI when V=1
,
Alistair Francis
,
17:59
[Qemu-riscv] [PATCH v1 18/27] target/riscv: Add Hypervisor trap return support
,
Alistair Francis
,
17:58
[Qemu-riscv] [PATCH v1 17/27] target/riscv: Add hypvervisor trap support
,
Alistair Francis
,
17:58
[Qemu-riscv] [PATCH v1 15/27] riscv: plic: Remove unused interrupt functions
,
Alistair Francis
,
17:58
[Qemu-riscv] [PATCH v1 11/27] target/riscv: Add background CSRs accesses
,
Alistair Francis
,
17:58
[Qemu-riscv] [PATCH v1 16/27] riscv: plic: Always set sip.SEIP bit for HS
,
Alistair Francis
,
17:58
[Qemu-riscv] [PATCH v1 13/27] target/ricsv: Flush the TLB on virtulisation mode changes
,
Alistair Francis
,
17:58
[Qemu-riscv] [PATCH v1 12/27] target/riscv: Add background register swapping function
,
Alistair Francis
,
17:58
[Qemu-riscv] [PATCH v1 10/27] target/riscv: Add Hypervisor CSR access functions
,
Alistair Francis
,
17:58
[Qemu-riscv] [PATCH v1 09/27] target/riscv: Add support for background interrupt setting
,
Alistair Francis
,
17:58
[Qemu-riscv] [PATCH v1 08/27] target/riscv: Create function to test if FP is enabled
,
Alistair Francis
,
17:58
[Qemu-riscv] [PATCH v1 00/27] Add RISC-V Hypervisor Extension
,
Alistair Francis
,
17:57
[Qemu-riscv] [PATCH v1 06/27] target/riscv: Dump Hypervisor registers if enabled
,
Alistair Francis
,
17:57
[Qemu-riscv] [PATCH v1 04/27] target/riscv: Add the force HS exception mode
,
Alistair Francis
,
17:57
[Qemu-riscv] [PATCH v1 07/27] target/riscv: Remove strict perm checking for CSR R/W
,
Alistair Francis
,
17:57
[Qemu-riscv] [PATCH v1 01/27] target/riscv: Don't set write permissions on dirty PTEs
,
Alistair Francis
,
17:57
[Qemu-riscv] [PATCH v1 03/27] target/riscv: Add the virtulisation mode
,
Alistair Francis
,
17:57
[Qemu-riscv] [PATCH v1 05/27] target/riscv: Add the Hypervisor CSRs to CPUState
,
Alistair Francis
,
17:57
[Qemu-riscv] [PATCH v1 02/27] target/riscv: Add the Hypervisor extension
,
Alistair Francis
,
17:57
June 06, 2019
Re: [Qemu-riscv] [Qemu-devel] Fwd: [address@hidden: atomic failures on qemu-system-riscv64]
,
Richard Henderson
,
22:51
[Qemu-riscv] RISC-V: Include ROM in QEMU
,
Alistair Francis
,
19:25
Re: [Qemu-riscv] [Qemu-devel] [PATCH for-4.1 2/2] target/riscv: Add support for -bios "firmware_filename" flag
,
Alistair Francis
,
19:10
Re: [Qemu-riscv] [Qemu-devel] [PATCHv4 4/6] RISC-V: Check PMP during Page Table Walks
,
Alistair Francis
,
19:05
Re: [Qemu-riscv] [PATCH v1 0/4] Miscellaneous patches from the RISC-V fork
,
Alistair Francis
,
15:09
Re: [Qemu-riscv] [Qemu-devel] [PATCH] riscv: virt: Correct pci "bus-range" encoding
,
Alistair Francis
,
15:09
Re: [Qemu-riscv] [Qemu-devel] [PATCH] riscv: virt: Correct pci "bus-range" encoding
,
Bin Meng
,
08:55
June 05, 2019
Re: [Qemu-riscv] [Qemu-devel] Fwd: [address@hidden: atomic failures on qemu-system-riscv64]
,
Palmer Dabbelt
,
19:18
Re: [Qemu-riscv] [Qemu-devel] [PATCHv4 4/6] RISC-V: Check PMP during Page Table Walks
,
Hesham Almatary
,
18:59
Re: [Qemu-riscv] [Qemu-devel] [PATCHv4 4/6] RISC-V: Check PMP during Page Table Walks
,
Alistair Francis
,
17:07
Re: [Qemu-riscv] [Qemu-devel] [PATCHv4 3/6] RISC-V: Check for the effective memory privilege mode during PMP checks
,
Alistair Francis
,
17:04
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