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[Qemu-riscv] [PULL 13/34] target/riscv: Restructure deprecatd CPUs
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From: |
Palmer Dabbelt |
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Subject: |
[Qemu-riscv] [PULL 13/34] target/riscv: Restructure deprecatd CPUs |
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Date: |
Fri, 28 Jun 2019 10:32:06 -0700 |
From: Alistair Francis <address@hidden>
Restructure the deprecated CPUs to make it clear in the code that these
are depreated. They are already marked as deprecated in
qemu-deprecated.texi. There are no functional changes.
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
target/riscv/cpu.c | 18 ++++++++++--------
target/riscv/cpu.h | 13 +++++++------
2 files changed, 17 insertions(+), 14 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 5b9fae608cca..17467c3d8705 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -559,18 +559,20 @@ static const TypeInfo riscv_cpu_type_infos[] = {
DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
#if defined(TARGET_RISCV32)
DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base32_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_09_1, rv32gcsu_priv1_09_1_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_10_0, rv32gcsu_priv1_10_0_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_RV32IMACU_NOMMU, rv32imacu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init)
+ DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init),
+ /* Depreacted */
+ DEFINE_CPU(TYPE_RISCV_CPU_RV32IMACU_NOMMU, rv32imacu_nommu_cpu_init),
+ DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_09_1, rv32gcsu_priv1_09_1_cpu_init),
+ DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_10_0, rv32gcsu_priv1_10_0_cpu_init)
#elif defined(TARGET_RISCV64)
DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base64_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_09_1, rv64gcsu_priv1_09_1_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_10_0, rv64gcsu_priv1_10_0_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_RV64IMACU_NOMMU, rv64imacu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64gcsu_priv1_10_0_cpu_init)
+ DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64gcsu_priv1_10_0_cpu_init),
+ /* Deprecated */
+ DEFINE_CPU(TYPE_RISCV_CPU_RV64IMACU_NOMMU, rv64imacu_nommu_cpu_init),
+ DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_09_1, rv64gcsu_priv1_09_1_cpu_init),
+ DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_10_0, rv64gcsu_priv1_10_0_cpu_init)
#endif
};
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 934b71c85e13..5eb9cab2ad62 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -35,16 +35,17 @@
#define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any")
#define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")
#define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")
-#define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9.1")
-#define TYPE_RISCV_CPU_RV32GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.10.0")
-#define TYPE_RISCV_CPU_RV32IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv32imacu-nommu")
-#define TYPE_RISCV_CPU_RV64GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.9.1")
-#define TYPE_RISCV_CPU_RV64GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.10.0")
-#define TYPE_RISCV_CPU_RV64IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv64imacu-nommu")
#define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
#define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
#define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34")
#define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
+/* Deprecated */
+#define TYPE_RISCV_CPU_RV32IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv32imacu-nommu")
+#define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9.1")
+#define TYPE_RISCV_CPU_RV32GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.10.0")
+#define TYPE_RISCV_CPU_RV64IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv64imacu-nommu")
+#define TYPE_RISCV_CPU_RV64GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.9.1")
+#define TYPE_RISCV_CPU_RV64GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.10.0")
#define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2))
#define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))
--
2.21.0
- [Qemu-riscv] [PULL 03/34] target/riscv: Fix PMP range boundary address bug, (continued)
- [Qemu-riscv] [PULL 03/34] target/riscv: Fix PMP range boundary address bug, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 05/34] RISC-V: Only Check PMP if MMU translation succeeds, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 04/34] target/riscv: Implement riscv_cpu_unassigned_access, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 10/34] RISC-V: Fix a PMP check with the correct access size, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 06/34] RISC-V: Raise access fault exceptions on PMP violations, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 07/34] RISC-V: Check for the effective memory privilege mode during PMP checks, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 12/34] RISC-V: Fix a memory leak when realizing a sifive_e, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 14/34] target/riscv: Add the privledge spec version 1.11.0, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 11/34] riscv: virt: Correct pci "bus-range" encoding, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 15/34] target/riscv: Add the mcountinhibit CSR, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 13/34] target/riscv: Restructure deprecatd CPUs,
Palmer Dabbelt <=
- [Qemu-riscv] [PULL 21/34] RISC-V: Add support for the Zifencei extension, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 19/34] target/riscv: Remove user version information, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 08/34] RISC-V: Check PMP during Page Table Walks, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 09/34] RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 17/34] qemu-deprecated.texi: Deprecate the RISC-V privledge spec 1.09.1, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 18/34] target/riscv: Require either I or E base extension, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 16/34] target/riscv: Set privledge spec 1.11.0 as default, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 22/34] RISC-V: Add support for the Zicsr extension, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 24/34] RISC-V: Update syscall list for 32-bit support., Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 26/34] disas/riscv: Disassemble reserved compressed encodings as illegal, Palmer Dabbelt, 2019/06/28