[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-riscv] [PATCH v5 15/30] riscv: hart: Add a "hartid-base" property
From: |
Bin Meng |
Subject: |
[Qemu-riscv] [PATCH v5 15/30] riscv: hart: Add a "hartid-base" property to RISC-V hart array |
Date: |
Thu, 22 Aug 2019 22:10:54 -0700 |
At present each hart's hartid in a RISC-V hart array is assigned
the same value of its index in the hart array. But for a system
that has multiple hart arrays, this is not the case any more.
Add a new "hartid-base" property so that hartid number can be
assigned based on the property value.
Signed-off-by: Bin Meng <address@hidden>
---
Changes in v5: None
Changes in v4:
- new patch to add a "hartid-base" property to RISC-V hart array
Changes in v3: None
Changes in v2: None
hw/riscv/riscv_hart.c | 8 +++++---
include/hw/riscv/riscv_hart.h | 1 +
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c
index 9deef869..52ab86a 100644
--- a/hw/riscv/riscv_hart.c
+++ b/hw/riscv/riscv_hart.c
@@ -27,6 +27,7 @@
static Property riscv_harts_props[] = {
DEFINE_PROP_UINT32("num-harts", RISCVHartArrayState, num_harts, 1),
+ DEFINE_PROP_UINT32("hartid-base", RISCVHartArrayState, hartid_base, 0),
DEFINE_PROP_STRING("cpu-type", RISCVHartArrayState, cpu_type),
DEFINE_PROP_END_OF_LIST(),
};
@@ -37,7 +38,7 @@ static void riscv_harts_cpu_reset(void *opaque)
cpu_reset(CPU(cpu));
}
-static void riscv_hart_realize(RISCVHartArrayState *s, int idx,
+static void riscv_hart_realize(RISCVHartArrayState *s, int idx, uint32_t
hartid,
char *cpu_type, Error **errp)
{
Error *err = NULL;
@@ -45,7 +46,7 @@ static void riscv_hart_realize(RISCVHartArrayState *s, int
idx,
object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx],
sizeof(RISCVCPU), cpu_type,
&error_abort, NULL);
- s->harts[idx].env.mhartid = idx;
+ s->harts[idx].env.mhartid = hartid;
qemu_register_reset(riscv_harts_cpu_reset, &s->harts[idx]);
object_property_set_bool(OBJECT(&s->harts[idx]), true,
"realized", &err);
@@ -58,12 +59,13 @@ static void riscv_hart_realize(RISCVHartArrayState *s, int
idx,
static void riscv_harts_realize(DeviceState *dev, Error **errp)
{
RISCVHartArrayState *s = RISCV_HART_ARRAY(dev);
+ uint32_t hartid = s->hartid_base;
int n;
s->harts = g_new0(RISCVCPU, s->num_harts);
for (n = 0; n < s->num_harts; n++) {
- riscv_hart_realize(s, n, s->cpu_type, errp);
+ riscv_hart_realize(s, n, hartid + n, s->cpu_type, errp);
}
}
diff --git a/include/hw/riscv/riscv_hart.h b/include/hw/riscv/riscv_hart.h
index 0671d88..1984e30 100644
--- a/include/hw/riscv/riscv_hart.h
+++ b/include/hw/riscv/riscv_hart.h
@@ -32,6 +32,7 @@ typedef struct RISCVHartArrayState {
/*< public >*/
uint32_t num_harts;
+ uint32_t hartid_base;
char *cpu_type;
RISCVCPU *harts;
} RISCVHartArrayState;
--
2.7.4
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 05/30] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead, (continued)
- [Qemu-riscv] [PATCH v5 06/30] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h, Bin Meng, 2019/08/23
- [Qemu-riscv] [PATCH v5 07/30] riscv: roms: Remove executable attribute of opensbi images, Bin Meng, 2019/08/23
- [Qemu-riscv] [PATCH v5 08/30] riscv: sifive_u: Remove the unnecessary include of prci header, Bin Meng, 2019/08/23
- [Qemu-riscv] [PATCH v5 10/30] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming, Bin Meng, 2019/08/23
- [Qemu-riscv] [PATCH v5 11/30] riscv: sifive_e: prci: Update the PRCI register block size, Bin Meng, 2019/08/23
- [Qemu-riscv] [PATCH v5 09/30] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}, Bin Meng, 2019/08/23
- [Qemu-riscv] [PATCH v5 14/30] riscv: hart: Extract hart realize to a separate routine, Bin Meng, 2019/08/23
- [Qemu-riscv] [PATCH v5 13/30] riscv: Add a sifive_cpu.h to include both E and U cpu type defines, Bin Meng, 2019/08/23
- [Qemu-riscv] [PATCH v5 15/30] riscv: hart: Add a "hartid-base" property to RISC-V hart array,
Bin Meng <=
- [Qemu-riscv] [PATCH v5 17/30] riscv: sifive_u: Set the minimum number of cpus to 2, Bin Meng, 2019/08/23
- [Qemu-riscv] [PATCH v5 18/30] riscv: sifive_u: Update PLIC hart topology configuration string, Bin Meng, 2019/08/23
- [Qemu-riscv] [PATCH v5 16/30] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC, Bin Meng, 2019/08/23
- [Qemu-riscv] [PATCH v5 23/30] riscv: sifive_u: Update UART base addresses and IRQs, Bin Meng, 2019/08/23
- [Qemu-riscv] [PATCH v5 20/30] riscv: sifive_u: Generate hfclk and rtcclk nodes, Bin Meng, 2019/08/23
- [Qemu-riscv] [PATCH v5 19/30] riscv: sifive: Implement PRCI model for FU540, Bin Meng, 2019/08/23