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qemu-riscv (date)
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Last Modified: Sat Aug 31 2019 22:54:07 -0400
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August 31, 2019
[Qemu-riscv] [PATCH v7 25/30] riscv: roms: Update default bios for sifive_u machine
,
Bin Meng
,
22:54
[Qemu-riscv] [PATCH v7 28/30] riscv: sifive_u: Fix broken GEM support
,
Bin Meng
,
22:54
[Qemu-riscv] [PATCH v7 26/30] riscv: sifive: Implement a model for SiFive FU540 OTP
,
Bin Meng
,
22:54
[Qemu-riscv] [PATCH v7 30/30] riscv: sifive_u: Update model and compatible strings in device tree
,
Bin Meng
,
22:54
[Qemu-riscv] [PATCH v7 29/30] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet
,
Bin Meng
,
22:54
[Qemu-riscv] [PATCH v7 27/30] riscv: sifive_u: Instantiate OTP memory with a serial number
,
Bin Meng
,
22:54
[Qemu-riscv] [PATCH v7 17/30] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC
,
Bin Meng
,
22:54
[Qemu-riscv] [PATCH v7 21/30] riscv: sifive_u: Add PRCI block to the SoC
,
Bin Meng
,
22:54
[Qemu-riscv] [PATCH v7 24/30] riscv: sifive_u: Change UART node name in device tree
,
Bin Meng
,
22:54
[Qemu-riscv] [PATCH v7 20/30] riscv: sifive_u: Generate hfclk and rtcclk nodes
,
Bin Meng
,
22:54
[Qemu-riscv] [PATCH v7 19/30] riscv: sifive: Implement PRCI model for FU540
,
Bin Meng
,
22:53
[Qemu-riscv] [PATCH v7 16/30] riscv: sifive_u: Set the minimum number of cpus to 2
,
Bin Meng
,
22:53
[Qemu-riscv] [PATCH v7 13/30] riscv: Add a sifive_cpu.h to include both E and U cpu type defines
,
Bin Meng
,
22:53
[Qemu-riscv] [PATCH v7 12/30] riscv: sifive_e: Drop sifive_mmio_emulate()
,
Bin Meng
,
22:53
[Qemu-riscv] [PATCH v7 10/30] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming
,
Bin Meng
,
22:53
[Qemu-riscv] [PATCH v7 09/30] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}
,
Bin Meng
,
22:53
[Qemu-riscv] [PATCH v7 18/30] riscv: sifive_u: Update PLIC hart topology configuration string
,
Bin Meng
,
22:53
[Qemu-riscv] [PATCH v7 23/30] riscv: sifive_u: Update UART base addresses and IRQs
,
Bin Meng
,
22:53
[Qemu-riscv] [PATCH v7 22/30] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes
,
Bin Meng
,
22:53
[Qemu-riscv] [PATCH v7 14/30] riscv: hart: Extract hart realize to a separate routine
,
Bin Meng
,
22:53
[Qemu-riscv] [PATCH v7 15/30] riscv: hart: Add a "hartid-base" property to RISC-V hart array
,
Bin Meng
,
22:53
[Qemu-riscv] [PATCH v7 11/30] riscv: sifive_e: prci: Update the PRCI register block size
,
Bin Meng
,
22:53
[Qemu-riscv] [PATCH v7 08/30] riscv: sifive_u: Remove the unnecessary include of prci header
,
Bin Meng
,
22:53
[Qemu-riscv] [PATCH v7 05/30] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead
,
Bin Meng
,
22:53
[Qemu-riscv] [PATCH v7 06/30] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h
,
Bin Meng
,
22:53
[Qemu-riscv] [PATCH v7 04/30] riscv: hw: Change create_fdt() to return void
,
Bin Meng
,
22:53
[Qemu-riscv] [PATCH v7 07/30] riscv: roms: Remove executable attribute of opensbi images
,
Bin Meng
,
22:53
[Qemu-riscv] [PATCH v7 00/30] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine
,
Bin Meng
,
22:53
[Qemu-riscv] [PATCH v7 02/30] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell
,
Bin Meng
,
22:53
[Qemu-riscv] [PATCH v7 01/30] riscv: hw: Remove superfluous "linux, phandle" property
,
Bin Meng
,
22:53
[Qemu-riscv] [PATCH v7 03/30] riscv: hw: Remove not needed PLIC properties in device tree
,
Bin Meng
,
22:53
August 30, 2019
Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 15/30] riscv: hart: Add a "hartid-base" property to RISC-V hart array
,
Alistair Francis
,
17:22
Re: [Qemu-riscv] [Qemu-devel] [PATCH] RISCV: support riscv vector extension 0.7.1
,
Alistair Francis
,
14:43
Re: [Qemu-riscv] [Qemu-devel] [PATCH] RISCV: support riscv vector extension 0.7.1
,
Alex Bennée
,
05:07
August 29, 2019
Re: [Qemu-riscv] [Qemu-devel] [PATCH] RISCV: support riscv vector extension 0.7.1
,
Alistair Francis
,
17:55
Re: [Qemu-riscv] [Qemu-devel] [PATCH] RISCV: support riscv vector extension 0.7.1
,
Aleksandar Markovic
,
14:32
Re: [Qemu-riscv] [PATCH] RISCV: support riscv vector extension 0.7.1
,
Chih-Min Chao
,
11:15
Re: [Qemu-riscv] [Qemu-devel] [PATCH] RISCV: support riscv vector extension 0.7.1
,
Richard Henderson
,
11:14
Re: [Qemu-riscv] [Qemu-devel] [PATCH] RISCV: support riscv vector extension 0.7.1
,
Richard Henderson
,
11:09
Re: [Qemu-riscv] [PATCH] RISCV: support riscv vector extension 0.7.1
,
liuzhiwei
,
09:41
Re: [Qemu-riscv] [Qemu-devel] [PATCH] RISCV: support riscv vector extension 0.7.1
,
liuzhiwei
,
09:40
Re: [Qemu-riscv] [Qemu-devel] [PATCH] RISCV: support riscv vector extension 0.7.1
,
liuzhiwei
,
08:51
Re: [Qemu-riscv] [Qemu-devel] [PATCH] RISCV: support riscv vector extension 0.7.1
,
liuzhiwei
,
08:06
August 28, 2019
Re: [Qemu-riscv] [Qemu-devel] [PATCH] RISCV: support riscv vector extension 0.7.1
,
Alistair Francis
,
17:38
Re: [Qemu-riscv] [Qemu-devel] [PATCH] RISCV: support riscv vector extension 0.7.1
,
Richard Henderson
,
16:43
Re: [Qemu-riscv] [Qemu-devel] [PATCH] RISCV: support riscv vector extension 0.7.1
,
Aleksandar Markovic
,
16:32
Re: [Qemu-riscv] [Qemu-devel] [PATCH] RISCV: support riscv vector extension 0.7.1
,
Richard Henderson
,
14:54
Re: [Qemu-riscv] [Qemu-devel] [PATCH] RISCV: support riscv vector extension 0.7.1
,
Richard Henderson
,
12:39
Re: [Qemu-riscv] [PATCH] RISCV: support riscv vector extension 0.7.1
,
Alex Bennée
,
05:08
[Qemu-riscv] [PATCH] RISCV: support riscv vector extension 0.7.1
,
liuzhiwei
,
03:03
August 27, 2019
Re: [Qemu-riscv] [PATCH v4] riscv: hmp: Add a command to show virtual memory mappings
,
Bin Meng
,
21:31
Re: [Qemu-riscv] [Qemu-devel] RISC-V: Vector && DSP Extension
,
Palmer Dabbelt
,
20:25
Re: [Qemu-riscv] [PATCH v1 02/28] target/riscv: Add the virtulisation mode
,
Alistair Francis
,
20:12
Re: [Qemu-riscv] [Qemu-devel] [PATCH v2] riscv: rv32: Root page table address can be larger than 32-bit
,
Palmer Dabbelt
,
19:37
Re: [Qemu-riscv] [PATCH v4] riscv: hmp: Add a command to show virtual memory mappings
,
Palmer Dabbelt
,
19:18
Re: [Qemu-riscv] [PATCH v1 05/28] target/riscv: Add the Hypervisor CSRs to CPUState
,
Chih-Min Chao
,
11:51
Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 03/28] target/riscv: Add the force HS exception mode
,
Chih-Min Chao
,
11:46
Re: [Qemu-riscv] [PATCH v1 02/28] target/riscv: Add the virtulisation mode
,
Chih-Min Chao
,
11:44
Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 01/28] target/riscv: Add the Hypervisor extension
,
Chih-Min Chao
,
11:26
[Qemu-riscv] [PATCH v6 25/30] riscv: roms: Update default bios for sifive_u machine
,
Bin Meng
,
11:00
[Qemu-riscv] [PATCH v6 17/30] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC
,
Bin Meng
,
10:59
[Qemu-riscv] [PATCH v6 26/30] riscv: sifive: Implement a model for SiFive FU540 OTP
,
Bin Meng
,
10:59
[Qemu-riscv] [PATCH v6 19/30] riscv: sifive: Implement PRCI model for FU540
,
Bin Meng
,
10:59
[Qemu-riscv] [PATCH v6 27/30] riscv: sifive_u: Instantiate OTP memory with a serial number
,
Bin Meng
,
10:59
[Qemu-riscv] [PATCH v6 28/30] riscv: sifive_u: Fix broken GEM support
,
Bin Meng
,
10:59
[Qemu-riscv] [PATCH v6 21/30] riscv: sifive_u: Add PRCI block to the SoC
,
Bin Meng
,
10:59
[Qemu-riscv] [PATCH v6 29/30] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet
,
Bin Meng
,
10:59
[Qemu-riscv] [PATCH v6 30/30] riscv: sifive_u: Update model and compatible strings in device tree
,
Bin Meng
,
10:59
[Qemu-riscv] [PATCH v6 23/30] riscv: sifive_u: Update UART base addresses and IRQs
,
Bin Meng
,
10:59
[Qemu-riscv] [PATCH v6 15/30] riscv: hart: Add a "hartid-base" property to RISC-V hart array
,
Bin Meng
,
10:59
[Qemu-riscv] [PATCH v6 18/30] riscv: sifive_u: Update PLIC hart topology configuration string
,
Bin Meng
,
10:59
[Qemu-riscv] [PATCH v6 20/30] riscv: sifive_u: Generate hfclk and rtcclk nodes
,
Bin Meng
,
10:59
[Qemu-riscv] [PATCH v6 22/30] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes
,
Bin Meng
,
10:59
[Qemu-riscv] [PATCH v6 14/30] riscv: hart: Extract hart realize to a separate routine
,
Bin Meng
,
10:59
[Qemu-riscv] [PATCH v6 16/30] riscv: sifive_u: Set the minimum number of cpus to 2
,
Bin Meng
,
10:59
[Qemu-riscv] [PATCH v6 24/30] riscv: sifive_u: Change UART node name in device tree
,
Bin Meng
,
10:59
[Qemu-riscv] [PATCH v6 13/30] riscv: Add a sifive_cpu.h to include both E and U cpu type defines
,
Bin Meng
,
10:59
[Qemu-riscv] [PATCH v6 09/30] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}
,
Bin Meng
,
10:59
[Qemu-riscv] [PATCH v6 12/30] riscv: sifive_e: Drop sifive_mmio_emulate()
,
Bin Meng
,
10:59
[Qemu-riscv] [PATCH v6 11/30] riscv: sifive_e: prci: Update the PRCI register block size
,
Bin Meng
,
10:59
[Qemu-riscv] [PATCH v6 10/30] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming
,
Bin Meng
,
10:59
[Qemu-riscv] [PATCH v6 07/30] riscv: roms: Remove executable attribute of opensbi images
,
Bin Meng
,
10:59
[Qemu-riscv] [PATCH v6 08/30] riscv: sifive_u: Remove the unnecessary include of prci header
,
Bin Meng
,
10:59
[Qemu-riscv] [PATCH v6 06/30] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h
,
Bin Meng
,
10:59
[Qemu-riscv] [PATCH v6 05/30] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead
,
Bin Meng
,
10:59
[Qemu-riscv] [PATCH v6 04/30] riscv: hw: Change create_fdt() to return void
,
Bin Meng
,
10:59
[Qemu-riscv] [PATCH v6 00/30] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine
,
Bin Meng
,
10:59
[Qemu-riscv] [PATCH v6 03/30] riscv: hw: Remove not needed PLIC properties in device tree
,
Bin Meng
,
10:59
[Qemu-riscv] [PATCH v6 02/30] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell
,
Bin Meng
,
10:59
[Qemu-riscv] [PATCH v6 01/30] riscv: hw: Remove superfluous "linux, phandle" property
,
Bin Meng
,
10:58
August 26, 2019
Re: [Qemu-riscv] [PATCH 0/2] riscv: Fix "-L" not working for bios image search path
,
Palmer Dabbelt
,
19:48
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/30] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine
,
Alistair Francis
,
17:38
Re: [Qemu-riscv] [PATCH v5 12/30] riscv: sifive_e: Drop sifive_mmio_emulate()
,
Alistair Francis
,
17:36
August 24, 2019
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/30] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine
,
Bin Meng
,
01:08
August 23, 2019
Re: [Qemu-riscv] [Qemu-devel] [PATCH v3] RISC-V: Select FPU gdb xml file based on the supported extensions
,
Alistair Francis
,
20:17
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 21/30] riscv: sifive_u: Add PRCI block to the SoC
,
Alistair Francis
,
19:57
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 19/30] riscv: sifive: Implement PRCI model for FU540
,
Alistair Francis
,
19:49
[Qemu-riscv] [PATCH v1 28/28] target/riscv: Allow enabling the Hypervisor extension
,
Alistair Francis
,
19:42
[Qemu-riscv] [PATCH v1 27/28] target/riscv: Add the MSTATUS_MPV_ISSET helper macro
,
Alistair Francis
,
19:42
[Qemu-riscv] [PATCH v1 26/28] target/riscv: Add support for the 32-bit MSTATUSH CSR
,
Alistair Francis
,
19:42
[Qemu-riscv] [PATCH v1 25/28] target/riscv: Call the second stage MMU in virtualisation mode
,
Alistair Francis
,
19:42
[Qemu-riscv] [PATCH v1 24/28] target/riscv: Implement second stage MMU
,
Alistair Francis
,
19:42
[Qemu-riscv] [PATCH v1 23/28] target/riscv: Allow specifying number of MMU stages
,
Alistair Francis
,
19:42
[Qemu-riscv] [PATCH v1 22/28] target/riscv: Allow specifying MMU stage
,
Alistair Francis
,
19:42
[Qemu-riscv] [PATCH v1 21/28] target/riscv: Respect MPRV and SPRV for floating point ops
,
Alistair Francis
,
19:42
[Qemu-riscv] [PATCH v1 17/28] target/riscv: Add Hypervisor trap return support
,
Alistair Francis
,
19:42
[Qemu-riscv] [PATCH v1 18/28] target/riscv: Add hfence instructions
,
Alistair Francis
,
19:42
[Qemu-riscv] [PATCH v1 20/28] target/riscv: Mark both sstatus and vsstatus as dirty
,
Alistair Francis
,
19:42
[Qemu-riscv] [PATCH v1 19/28] target/riscv: Disable guest FP support based on virtual status
,
Alistair Francis
,
19:42
[Qemu-riscv] [PATCH v1 16/28] target/riscv: Add hypvervisor trap support
,
Alistair Francis
,
19:42
[Qemu-riscv] [PATCH v1 15/28] riscv: plic: Always set sip.SEIP bit for HS
,
Alistair Francis
,
19:42
[Qemu-riscv] [PATCH v1 14/28] target/riscv: Generate illegal instruction on WFI when V=1
,
Alistair Francis
,
19:42
[Qemu-riscv] [PATCH v1 13/28] target/ricsv: Flush the TLB on virtulisation mode changes
,
Alistair Francis
,
19:42
[Qemu-riscv] [PATCH v1 12/28] target/riscv: Add support for virtual interrupt setting
,
Alistair Francis
,
19:42
[Qemu-riscv] [PATCH v1 10/28] target/riscv: Convert mie and mstatus to pointers
,
Alistair Francis
,
19:42
[Qemu-riscv] [PATCH v1 09/28] target/riscv: Add Hypervisor virtual CSRs accesses
,
Alistair Francis
,
19:42
[Qemu-riscv] [PATCH v1 11/28] target/riscv: Add background register swapping function
,
Alistair Francis
,
19:42
[Qemu-riscv] [PATCH v1 07/28] target/riscv: Dump Hypervisor registers if enabled
,
Alistair Francis
,
19:41
[Qemu-riscv] [PATCH v1 08/28] target/riscv: Add Hypervisor CSR access functions
,
Alistair Francis
,
19:41
[Qemu-riscv] [PATCH v1 06/28] target/riscv: Print priv and virt in disas log
,
Alistair Francis
,
19:41
[Qemu-riscv] [PATCH v1 05/28] target/riscv: Add the Hypervisor CSRs to CPUState
,
Alistair Francis
,
19:41
[Qemu-riscv] [PATCH v1 03/28] target/riscv: Add the force HS exception mode
,
Alistair Francis
,
19:41
[Qemu-riscv] [PATCH v1 04/28] target/riscv: Fix CSR perm checking for HS mode
,
Alistair Francis
,
19:41
[Qemu-riscv] [PATCH v1 00/28] Add RISC-V Hypervisor Extension v0.4
,
Alistair Francis
,
19:41
[Qemu-riscv] [PATCH v1 02/28] target/riscv: Add the virtulisation mode
,
Alistair Francis
,
19:41
[Qemu-riscv] [PATCH v1 01/28] target/riscv: Add the Hypervisor extension
,
Alistair Francis
,
19:41
Re: [Qemu-riscv] [PATCH v3] RISC-V: Select FPU gdb xml file based on the supported extensions
,
Jim Wilson
,
18:44
[Qemu-riscv] [Qemu-devel] [PATCH 3/9] exec: Replace DEVICE_LITTLE_ENDIAN with MO_LE
,
Tony Nguyen
,
15:41
[Qemu-riscv] [Qemu-devel] [PATCH 2/9] exec: Replace DEVICE_NATIVE_ENDIAN with MO_TE
,
Tony Nguyen
,
15:41
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 17/30] riscv: sifive_u: Set the minimum number of cpus to 2
,
Alistair Francis
,
14:38
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 15/30] riscv: hart: Add a "hartid-base" property to RISC-V hart array
,
Alistair Francis
,
14:35
[Qemu-riscv] [Qemu-devel] [PATCH v9 01/20] tcg: TCGMemOp is now accelerator independent MemOp
,
Tony Nguyen
,
14:09
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/30] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine
,
Alistair Francis
,
13:45
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 05/30] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead
,
Alistair Francis
,
13:43
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 06/30] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h
,
Alistair Francis
,
13:42
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 16/30] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC
,
Alistair Francis
,
13:41
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/30] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine
,
Alistair Francis
,
13:29
Re: [Qemu-riscv] [Qemu-devel] [PATCH v4 7/7] target/riscv: Use TB_FLAGS_MSTATUS_FS for floating point
,
Alistair Francis
,
11:48
Re: [Qemu-riscv] [Qemu-devel] [PATCH v4 7/7] target/riscv: Use TB_FLAGS_MSTATUS_FS for floating point
,
Peter Maydell
,
11:44
[Qemu-riscv] [PATCH v4 7/7] target/riscv: Use TB_FLAGS_MSTATUS_FS for floating point
,
Alistair Francis
,
11:25
[Qemu-riscv] [PATCH v4 6/7] target/riscv: Fix mstatus dirty mask
,
Alistair Francis
,
11:25
[Qemu-riscv] [PATCH v4 5/7] target/riscv: Use both register name and ABI name
,
Alistair Francis
,
11:25
[Qemu-riscv] [PATCH v4 4/7] target/riscv: Update the Hypervisor CSRs to v0.4
,
Alistair Francis
,
11:25
[Qemu-riscv] [PATCH v4 3/7] target/riscv: Create function to test if FP is enabled
,
Alistair Francis
,
11:25
[Qemu-riscv] [PATCH v4 0/7] RISC-V: Hypervisor prep work part 2
,
Alistair Francis
,
11:24
[Qemu-riscv] [PATCH v4 2/7] riscv: plic: Remove unused interrupt functions
,
Alistair Francis
,
11:24
[Qemu-riscv] [PATCH v4 1/7] target/riscv: Don't set write permissions on dirty PTEs
,
Alistair Francis
,
11:24
Re: [Qemu-riscv] [PATCH v3 7/7] target/riscv: Convert mip to target_ulong
,
Alistair Francis
,
11:23
[Qemu-riscv] [PATCH v5 25/30] riscv: roms: Update default bios for sifive_u machine
,
Bin Meng
,
01:12
[Qemu-riscv] [PATCH v5 28/30] riscv: sifive_u: Fix broken GEM support
,
Bin Meng
,
01:12
[Qemu-riscv] [PATCH v5 29/30] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet
,
Bin Meng
,
01:12
[Qemu-riscv] [PATCH v5 26/30] riscv: sifive: Implement a model for SiFive FU540 OTP
,
Bin Meng
,
01:12
[Qemu-riscv] [PATCH v5 30/30] riscv: sifive_u: Update model and compatible strings in device tree
,
Bin Meng
,
01:12
[Qemu-riscv] [PATCH v5 24/30] riscv: sifive_u: Change UART node name in device tree
,
Bin Meng
,
01:11
[Qemu-riscv] [PATCH v5 22/30] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes
,
Bin Meng
,
01:11
[Qemu-riscv] [PATCH v5 21/30] riscv: sifive_u: Add PRCI block to the SoC
,
Bin Meng
,
01:11
[Qemu-riscv] [PATCH v5 19/30] riscv: sifive: Implement PRCI model for FU540
,
Bin Meng
,
01:11
[Qemu-riscv] [PATCH v5 20/30] riscv: sifive_u: Generate hfclk and rtcclk nodes
,
Bin Meng
,
01:11
[Qemu-riscv] [PATCH v5 23/30] riscv: sifive_u: Update UART base addresses and IRQs
,
Bin Meng
,
01:11
[Qemu-riscv] [PATCH v5 16/30] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC
,
Bin Meng
,
01:11
[Qemu-riscv] [PATCH v5 18/30] riscv: sifive_u: Update PLIC hart topology configuration string
,
Bin Meng
,
01:11
[Qemu-riscv] [PATCH v5 17/30] riscv: sifive_u: Set the minimum number of cpus to 2
,
Bin Meng
,
01:11
[Qemu-riscv] [PATCH v5 15/30] riscv: hart: Add a "hartid-base" property to RISC-V hart array
,
Bin Meng
,
01:11
[Qemu-riscv] [PATCH v5 13/30] riscv: Add a sifive_cpu.h to include both E and U cpu type defines
,
Bin Meng
,
01:11
[Qemu-riscv] [PATCH v5 14/30] riscv: hart: Extract hart realize to a separate routine
,
Bin Meng
,
01:11
[Qemu-riscv] [PATCH v5 09/30] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}
,
Bin Meng
,
01:11
[Qemu-riscv] [PATCH v5 11/30] riscv: sifive_e: prci: Update the PRCI register block size
,
Bin Meng
,
01:11
[Qemu-riscv] [PATCH v5 10/30] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming
,
Bin Meng
,
01:11
[Qemu-riscv] [PATCH v5 08/30] riscv: sifive_u: Remove the unnecessary include of prci header
,
Bin Meng
,
01:11
[Qemu-riscv] [PATCH v5 07/30] riscv: roms: Remove executable attribute of opensbi images
,
Bin Meng
,
01:11
[Qemu-riscv] [PATCH v5 06/30] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h
,
Bin Meng
,
01:11
[Qemu-riscv] [PATCH v5 05/30] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead
,
Bin Meng
,
01:11
[Qemu-riscv] [PATCH v5 04/30] riscv: hw: Change create_fdt() to return void
,
Bin Meng
,
01:11
[Qemu-riscv] [PATCH v5 02/30] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell
,
Bin Meng
,
01:11
[Qemu-riscv] [PATCH v5 00/30] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine
,
Bin Meng
,
01:11
[Qemu-riscv] [PATCH v5 03/30] riscv: hw: Remove not needed PLIC properties in device tree
,
Bin Meng
,
01:11
[Qemu-riscv] [PATCH v5 01/30] riscv: hw: Remove superfluous "linux, phandle" property
,
Bin Meng
,
01:11
August 22, 2019
Re: [Qemu-riscv] [Qemu-devel] [PATCH v4 13/28] riscv: hart: Add a "hartid-base" property to RISC-V hart array
,
Bin Meng
,
21:57
Re: [Qemu-riscv] [Qemu-devel] [PATCH v4 24/28] riscv: sifive: Implement a model for SiFive FU540 OTP
,
Alistair Francis
,
18:45
Re: [Qemu-riscv] [Qemu-devel] [PATCH v4 13/28] riscv: hart: Add a "hartid-base" property to RISC-V hart array
,
Alistair Francis
,
18:44
Re: [Qemu-riscv] [Qemu-devel] [PATCH v4 27/28] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet
,
Alistair Francis
,
18:43
Re: [Qemu-riscv] [Qemu-devel] RISCV: when will the CLIC be ready?
,
Alistair Francis
,
18:42
Re: [Qemu-riscv] [Qemu-devel] RISC-V: Vector && DSP Extension
,
Alistair Francis
,
18:41
August 21, 2019
Re: [Qemu-riscv] [Qemu-devel] RISC-V: Vector && DSP Extension
,
liuzhiwei
,
21:56
Re: [Qemu-riscv] [Qemu-devel] RISC-V: Vector && DSP Extension
,
Jonathan Behrens
,
19:11
Re: [Qemu-riscv] [Qemu-devel] RISC-V: Vector && DSP Extension
,
Palmer Dabbelt
,
15:31
Re: [Qemu-riscv] [Qemu-devel] [PATCH v2] target/riscv: Hardwire mcounter.TM and upper bits of [m|s]counteren
,
Palmer Dabbelt
,
13:37
[Qemu-riscv] [Qemu-devel] [PATCH v8 02/21] tcg: TCGMemOp is now accelerator independent MemOp
,
Tony Nguyen
,
13:13
Re: [Qemu-riscv] [PATCH v2] RISC-V: Select FPU gdb xml file based on the supported extensions
,
Georg Kotheimer
,
12:35
[Qemu-riscv] [PATCH v3] RISC-V: Select FPU gdb xml file based on the supported extensions
,
Georg Kotheimer
,
12:35
August 20, 2019
Re: [Qemu-riscv] [Qemu-devel] RISCV: when will the CLIC be ready?
,
liuzhiwei
,
23:39
Re: [Qemu-riscv] [Qemu-devel] RISCV: when will the CLIC be ready?
,
liuzhiwei
,
23:07
Re: [Qemu-riscv] [Qemu-devel] [PATCH v2] RISC-V: Select FPU gdb xml file based on the supported extensions
,
Richard Henderson
,
16:22
Re: [Qemu-riscv] [PATCH v2] RISC-V: Select FPU gdb xml file based on the supported extensions
,
Jim Wilson
,
16:06
Re: [Qemu-riscv] [Qemu-devel] [PATCH 2/2] riscv: Resolve full path of the given bios image
,
Alistair Francis
,
14:44
Re: [Qemu-riscv] [Qemu-devel] [PATCH v4 20/28] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes
,
Alistair Francis
,
14:31
[Qemu-riscv] [PATCH v2] RISC-V: Select FPU gdb xml file based on the supported extensions
,
Georg Kotheimer
,
10:41
August 19, 2019
Re: [Qemu-riscv] [Qemu-devel] [qemu-s390x] [PATCH v7 33/42] exec: Replace device_endian with MemOp
,
Edgar E. Iglesias
,
23:54
Re: [Qemu-riscv] [Qemu-devel] RISCV: when will the CLIC be ready?
,
Bin Meng
,
21:21
Re: [Qemu-riscv] [Qemu-devel] [qemu-s390x] [PATCH v7 33/42] exec: Replace device_endian with MemOp
,
Richard Henderson
,
17:01
Re: [Qemu-riscv] [Qemu-devel] [PATCH v4 18/28] riscv: sifive_u: Generate hfclk and rtcclk nodes
,
Alistair Francis
,
16:27
Re: [Qemu-riscv] [Qemu-devel] [PATCH v4 17/28] riscv: sifive: Implement PRCI model for FU540
,
Alistair Francis
,
16:25
Re: [Qemu-riscv] [Qemu-devel] [PATCH v4 05/28] riscv: roms: Remove executable attribute of opensbi images
,
Alistair Francis
,
16:12
Re: [Qemu-riscv] [Qemu-devel] RISCV: when will the CLIC be ready?
,
Alistair Francis
,
15:00
Re: [Qemu-riscv] [qemu-s390x] [Qemu-devel] [PATCH v7 33/42] exec: Replace device_endian with MemOp
,
Paolo Bonzini
,
14:29
Re: [Qemu-riscv] [qemu-s390x] [Qemu-devel] [PATCH v7 33/42] exec: Replace device_endian with MemOp
,
Paolo Bonzini
,
14:28
Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 25/42] hw/misc: Declare device little or big endian
,
Paolo Bonzini
,
14:26
Re: [Qemu-riscv] [Qemu-devel] RISCV: when will the CLIC be ready?
,
Chih-Min Chao
,
12:38
Re: [Qemu-riscv] [Qemu-devel] RISCV: when will the CLIC be ready?
,
liuzhiwei
,
09:44
[Qemu-riscv] [PULL 11/12] target/riscv: rationalise softfloat includes
,
Alex Bennée
,
08:17
Re: [Qemu-riscv] [Qemu-devel] [PATCH v2] riscv: rv32: Root page table address can be larger than 32-bit
,
Bin Meng
,
02:01
Re: [Qemu-riscv] [PATCH v4] riscv: hmp: Add a command to show virtual memory mappings
,
Bin Meng
,
02:00
[Qemu-riscv] [PATCH v4 24/28] riscv: sifive: Implement a model for SiFive FU540 OTP
,
Bin Meng
,
01:13
[Qemu-riscv] [PATCH v4 23/28] riscv: roms: Update default bios for sifive_u machine
,
Bin Meng
,
01:13
[Qemu-riscv] [PATCH v4 21/28] riscv: sifive_u: Update UART base addresses and IRQs
,
Bin Meng
,
01:13
[Qemu-riscv] [PATCH v4 28/28] riscv: sifive_u: Update model and compatible strings in device tree
,
Bin Meng
,
01:13
[Qemu-riscv] [PATCH v4 22/28] riscv: sifive_u: Change UART node name in device tree
,
Bin Meng
,
01:12
[Qemu-riscv] [PATCH v4 17/28] riscv: sifive: Implement PRCI model for FU540
,
Bin Meng
,
01:12
[Qemu-riscv] [PATCH v4 27/28] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet
,
Bin Meng
,
01:12
[Qemu-riscv] [PATCH v4 26/28] riscv: sifive_u: Fix broken GEM support
,
Bin Meng
,
01:12
[Qemu-riscv] [PATCH v4 19/28] riscv: sifive_u: Add PRCI block to the SoC
,
Bin Meng
,
01:12
[Qemu-riscv] [PATCH v4 25/28] riscv: sifive_u: Instantiate OTP memory with a serial number
,
Bin Meng
,
01:12
[Qemu-riscv] [PATCH v4 15/28] riscv: sifive_u: Set the minimum number of cpus to 2
,
Bin Meng
,
01:12
[Qemu-riscv] [PATCH v4 20/28] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes
,
Bin Meng
,
01:12
[Qemu-riscv] [PATCH v4 16/28] riscv: sifive_u: Update PLIC hart topology configuration string
,
Bin Meng
,
01:12
[Qemu-riscv] [PATCH v4 13/28] riscv: hart: Add a "hartid-base" property to RISC-V hart array
,
Bin Meng
,
01:12
[Qemu-riscv] [PATCH v4 11/28] riscv: Add a sifive_cpu.h to include both E and U cpu type defines
,
Bin Meng
,
01:12
[Qemu-riscv] [PATCH v4 18/28] riscv: sifive_u: Generate hfclk and rtcclk nodes
,
Bin Meng
,
01:12
[Qemu-riscv] [PATCH v4 14/28] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC
,
Bin Meng
,
01:12
[Qemu-riscv] [PATCH v4 12/28] riscv: hart: Extract hart realize to a separate routine
,
Bin Meng
,
01:12
[Qemu-riscv] [PATCH v4 09/28] riscv: sifive_e: prci: Update the PRCI register block size
,
Bin Meng
,
01:12
[Qemu-riscv] [PATCH v4 07/28] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}
,
Bin Meng
,
01:12
[Qemu-riscv] [PATCH v4 06/28] riscv: sifive_u: Remove the unnecessary include of prci header
,
Bin Meng
,
01:12
[Qemu-riscv] [PATCH v4 00/28] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine
,
Bin Meng
,
01:12
[Qemu-riscv] [PATCH v4 08/28] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming
,
Bin Meng
,
01:12
[Qemu-riscv] [PATCH v4 04/28] riscv: hw: Change create_fdt() to return void
,
Bin Meng
,
01:12
[Qemu-riscv] [PATCH v4 02/28] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell
,
Bin Meng
,
01:12
[Qemu-riscv] [PATCH v4 05/28] riscv: roms: Remove executable attribute of opensbi images
,
Bin Meng
,
01:12
[Qemu-riscv] [PATCH v4 03/28] riscv: hw: Remove not needed PLIC properties in device tree
,
Bin Meng
,
01:12
[Qemu-riscv] [PATCH v4 01/28] riscv: hw: Remove superfluous "linux, phandle" property
,
Bin Meng
,
01:12
August 18, 2019
Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 11/42] memory: Access MemoryRegion with MemOp
,
Philippe Mathieu-Daudé
,
17:44
Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 38/42] memory: Single byte swap along the I/O path
,
Richard Henderson
,
08:46
Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 37/42] cputlb: Replace size and endian operands for MemOp
,
Richard Henderson
,
08:38
Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 36/42] memory: Access MemoryRegion with endianness
,
Richard Henderson
,
08:24
Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE
,
Richard Henderson
,
05:13
August 16, 2019
Re: [Qemu-riscv] [Qemu-devel] RISCV: when will the CLIC be ready?
,
Alistair Francis
,
13:33
Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 7/7] target/riscv: Convert mip to target_ulong
,
Bin Meng
,
09:59
Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 6/7] target/riscv: Fix mstatus dirty mask
,
Bin Meng
,
09:59
Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 5/7] target/riscv: Use both register name and ABI name
,
Bin Meng
,
09:59
Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 4/7] target/riscv: Update the Hypervisor CSRs to v0.4
,
Bin Meng
,
09:59
Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 3/7] target/riscv: Create function to test if FP is enabled
,
Bin Meng
,
09:59
Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 1/7] target/riscv: Don't set write permissions on dirty PTEs
,
Bin Meng
,
09:59
Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 2/7] riscv: plic: Remove unused interrupt functions
,
Bin Meng
,
09:59
[Qemu-riscv] [Qemu-devel] [PATCH v7 33/42] exec: Replace device_endian with MemOp
,
tony.nguyen
,
09:57
[Qemu-riscv] [Qemu-devel] [PATCH v7 33/42] exec: Replace device_endian with MemOp
,
tony.nguyen
,
09:57
[Qemu-riscv] [Qemu-devel] [PATCH v7 33/42] exec: Replace device_endian with MemOp
,
tony.nguyen
,
09:57
[Qemu-riscv] [PATCH 2/2] riscv: Resolve full path of the given bios image
,
Bin Meng
,
09:09
[Qemu-riscv] [PATCH 1/2] riscv: Add a helper routine for finding firmware
,
Bin Meng
,
09:09
[Qemu-riscv] [PATCH 0/2] riscv: Fix "-L" not working for bios image search path
,
Bin Meng
,
09:09
Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE
,
David Gibson
,
08:05
Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE
,
Peter Maydell
,
08:02
Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE
,
tony.nguyen
,
07:37
Re: [Qemu-riscv] [qemu-s390x] [Qemu-devel] [PATCH v7 33/42] exec: Replace device_endian with MemOp
,
Thomas Huth
,
06:16
Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 27/42] hw/pci-host: Declare device little or big endian
,
Philippe Mathieu-Daudé
,
06:06
Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 25/42] hw/misc: Declare device little or big endian
,
Philippe Mathieu-Daudé
,
06:04
Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 24/42] hw/isa: Declare device little or big endian
,
Philippe Mathieu-Daudé
,
06:02
Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE
,
Philippe Mathieu-Daudé
,
05:58
Re: [Qemu-riscv] [Qemu-devel] [PULL 04/32] target/riscv: Implement riscv_cpu_unassigned_access
,
Peter Maydell
,
04:57
[Qemu-riscv] [Qemu-devel] [PATCH v7 38/42] memory: Single byte swap along the I/O path
,
tony.nguyen
,
03:40
[Qemu-riscv] [Qemu-devel] [PATCH v7 42/42] target/sparc: sun4u Invert Endian TTE bit
,
tony.nguyen
,
03:40
[Qemu-riscv] [Qemu-devel] [PATCH v7 41/42] target/sparc: Add TLB entry with attributes
,
tony.nguyen
,
03:39
[Qemu-riscv] [Qemu-devel] [PATCH v7 40/42] cputlb: Byte swap memory transaction attribute
,
tony.nguyen
,
03:39
[Qemu-riscv] [Qemu-devel] [PATCH v7 36/42] memory: Access MemoryRegion with endianness
,
tony.nguyen
,
03:39
[Qemu-riscv] [Qemu-devel] [PATCH v7 39/42] cpu: TLB_FLAGS_MASK bit to force memory slow path
,
tony.nguyen
,
03:39
[Qemu-riscv] [Qemu-devel] [PATCH v7 37/42] cputlb: Replace size and endian operands for MemOp
,
tony.nguyen
,
03:38
[Qemu-riscv] [Qemu-devel] [PATCH v7 31/42] build: Correct non-common common-obj-* to obj-*
,
tony.nguyen
,
03:38
[Qemu-riscv] [Qemu-devel] [PATCH v7 35/42] exec: Delete DEVICE_HOST_ENDIAN
,
tony.nguyen
,
03:37
[Qemu-riscv] [Qemu-devel] [PATCH v7 34/42] exec: Delete device_endian
,
tony.nguyen
,
03:37
[Qemu-riscv] [Qemu-devel] [PATCH v7 32/42] exec: Map device_endian onto MemOp
,
tony.nguyen
,
03:36
[Qemu-riscv] [Qemu-devel] [PATCH v7 30/42] hw/timer: Declare device little or big endian
,
tony.nguyen
,
03:36
[Qemu-riscv] [Qemu-devel] [PATCH v7 29/42] hw/ssi: Declare device little or big endian
,
tony.nguyen
,
03:36
[Qemu-riscv] [Qemu-devel] [PATCH v7 27/42] hw/pci-host: Declare device little or big endian
,
tony.nguyen
,
03:35
[Qemu-riscv] [Qemu-devel] [PATCH v7 26/42] hw/net: Declare device little or big endian
,
tony.nguyen
,
03:35
[Qemu-riscv] [Qemu-devel] [PATCH v7 28/42] hw/sd: Declare device little or big endian
,
tony.nguyen
,
03:35
[Qemu-riscv] [Qemu-devel] [PATCH v7 25/42] hw/misc: Declare device little or big endian
,
tony.nguyen
,
03:35
[Qemu-riscv] [Qemu-devel] [PATCH v7 24/42] hw/isa: Declare device little or big endian
,
tony.nguyen
,
03:34
[Qemu-riscv] [Qemu-devel] [PATCH v7 23/42] hw/intc: Declare device little or big endian
,
tony.nguyen
,
03:34
[Qemu-riscv] [Qemu-devel] [PATCH v7 22/42] hw/input: Declare device little or big endian
,
tony.nguyen
,
03:34
[Qemu-riscv] [Qemu-devel] [PATCH v7 21/42] hw/i2c: Declare device little or big endian
,
tony.nguyen
,
03:33
[Qemu-riscv] [Qemu-devel] [PATCH v7 17/42] hw/char: Declare device little or big endian
,
tony.nguyen
,
03:33
[Qemu-riscv] [Qemu-devel] [PATCH v7 20/42] hw/gpio: Declare device little or big endian
,
tony.nguyen
,
03:33
[Qemu-riscv] [Qemu-devel] [PATCH v7 19/42] hw/dma: Declare device little or big endian
,
tony.nguyen
,
03:33
[Qemu-riscv] [Qemu-devel] [PATCH v7 18/42] hw/display: Declare device little or big endian
,
tony.nguyen
,
03:33
[Qemu-riscv] [Qemu-devel] [PATCH v7 16/42] hw/block: Declare device little or big endian
,
tony.nguyen
,
03:33
[Qemu-riscv] [Qemu-devel] [PATCH v7 15/42] hw/audio: Declare device little or big endian
,
tony.nguyen
,
03:32
[Qemu-riscv] [Qemu-devel] [PATCH v7 14/42] exec: Hard code size with MO_{8|16|32|64}
,
tony.nguyen
,
03:31
[Qemu-riscv] [Qemu-devel] [PATCH v7 13/42] target/mips: Hard code size with MO_{8|16|32|64}
,
tony.nguyen
,
03:31
[Qemu-riscv] [Qemu-devel] [PATCH v7 11/42] memory: Access MemoryRegion with MemOp
,
tony.nguyen
,
03:31
[Qemu-riscv] [Qemu-devel] [PATCH v7 12/42] hw/s390x: Hard code size with MO_{8|16|32|64}
,
tony.nguyen
,
03:31
[Qemu-riscv] [Qemu-devel] [PATCH v7 09/42] exec: Access MemoryRegion with MemOp
,
tony.nguyen
,
03:30
[Qemu-riscv] [Qemu-devel] [PATCH v7 10/42] cputlb: Access MemoryRegion with MemOp
,
tony.nguyen
,
03:30
[Qemu-riscv] [Qemu-devel] [PATCH v7 08/42] hw/vfio: Access MemoryRegion with MemOp
,
tony.nguyen
,
03:30
[Qemu-riscv] [Qemu-devel] [PATCH v7 07/42] hw/virtio: Access MemoryRegion with MemOp
,
tony.nguyen
,
03:29
[Qemu-riscv] [Qemu-devel] [PATCH v7 05/42] hw/s390x: Access MemoryRegion with MemOp
,
tony.nguyen
,
03:28
[Qemu-riscv] [Qemu-devel] [PATCH v7 06/42] hw/intc/armv7m_nic: Access MemoryRegion with MemOp
,
tony.nguyen
,
03:28
[Qemu-riscv] [Qemu-devel] [PATCH v7 04/42] target/mips: Access MemoryRegion with MemOp
,
tony.nguyen
,
03:27
[Qemu-riscv] [Qemu-devel] [PATCH v7 02/42] tcg: TCGMemOp is now accelerator independent MemOp
,
tony.nguyen
,
03:27
[Qemu-riscv] [Qemu-devel] [PATCH v7 03/42] memory: Introduce size_memop
,
tony.nguyen
,
03:27
[Qemu-riscv] [Qemu-devel] [PATCH v7 01/42] configure: Define TARGET_ALIGNED_ONLY
,
tony.nguyen
,
03:09
[Qemu-riscv] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE
,
tony.nguyen
,
02:29
August 15, 2019
[Qemu-riscv] RISCV: when will the CLIC be ready?
,
liuzhiwei
,
23:39
Re: [Qemu-riscv] [Qemu-devel] [PULL 04/32] target/riscv: Implement riscv_cpu_unassigned_access
,
Palmer Dabbelt
,
18:17
Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 0/7] RISC-V: Hypervisor prep work part 2
,
no-reply
,
18:13
Re: [Qemu-riscv] [Qemu-devel] [PULL 04/32] target/riscv: Implement riscv_cpu_unassigned_access
,
Alistair Francis
,
17:43
Re: [Qemu-riscv] [Qemu-devel] RISC-V: Vector && DSP Extension
,
Alistair Francis
,
17:41
[Qemu-riscv] [PATCH v3 7/7] target/riscv: Convert mip to target_ulong
,
Alistair Francis
,
17:38
[Qemu-riscv] [PATCH v3 6/7] target/riscv: Fix mstatus dirty mask
,
Alistair Francis
,
17:38
[Qemu-riscv] [PATCH v3 5/7] target/riscv: Use both register name and ABI name
,
Alistair Francis
,
17:38
[Qemu-riscv] [PATCH v3 4/7] target/riscv: Update the Hypervisor CSRs to v0.4
,
Alistair Francis
,
17:38
[Qemu-riscv] [PATCH v3 2/7] riscv: plic: Remove unused interrupt functions
,
Alistair Francis
,
17:38
[Qemu-riscv] [PATCH v3 3/7] target/riscv: Create function to test if FP is enabled
,
Alistair Francis
,
17:38
[Qemu-riscv] [PATCH v3 1/7] target/riscv: Don't set write permissions on dirty PTEs
,
Alistair Francis
,
17:38
[Qemu-riscv] [PATCH v3 0/7] RISC-V: Hypervisor prep work part 2
,
Alistair Francis
,
17:38
Re: [Qemu-riscv] [Qemu-devel] RISC-V: Vector && DSP Extension
,
Aleksandar Markovic
,
06:33
Re: [Qemu-riscv] [Qemu-devel] RISC-V: Vector && DSP Extension
,
Peter Maydell
,
05:08
Re: [Qemu-riscv] [Qemu-devel] RISC-V: Vector && DSP Extension
,
Aleksandar Markovic
,
04:53
August 14, 2019
Re: [Qemu-riscv] [Qemu-devel] [PATCH v2] target/riscv: Hardwire mcounter.TM and upper bits of [m|s]counteren
,
Jonathan Behrens
,
23:20
Re: [Qemu-riscv] [Qemu-devel] [PATCH 1/3] riscv: sifive_u: Add support for loading initrd
,
Palmer Dabbelt
,
21:53
Re: [Qemu-riscv] [Qemu-devel] [PATCH 1/3] riscv: sifive_u: Add support for loading initrd
,
Bin Meng
,
21:31
Re: [Qemu-riscv] [Qemu-devel] [PATCH v2] RISC-V: Ignore the S and U letters when formatting ISA strings
,
Alistair Francis
,
14:31
Re: [Qemu-riscv] [PATCH-4.2 v2 5/5] target/riscv: Fix Floating Point register names
,
Palmer Dabbelt
,
14:07
Re: [Qemu-riscv] [Qemu-devel] [PATCH 1/3] riscv: sifive_u: Add support for loading initrd
,
Palmer Dabbelt
,
13:06
Re: [Qemu-riscv] [PATCH] riscv: hmp: Add a command to show virtual memory mappings
,
Bin Meng
,
11:36
[Qemu-riscv] [PATCH v4] riscv: hmp: Add a command to show virtual memory mappings
,
Bin Meng
,
11:33
Re: [Qemu-riscv] [Qemu-devel] [PATCH v2] riscv: rv32: Root page table address can be larger than 32-bit
,
Bin Meng
,
05:47
Re: [Qemu-riscv] [Qemu-devel] [PATCH] riscv: sifive_e: Correct various SoC IP block sizes
,
Bin Meng
,
05:34
Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 6/7] target/riscv: rationalise softfloat includes
,
Alex Bennée
,
05:20
August 13, 2019
Re: [Qemu-riscv] [PATCH] riscv: hmp: Add a command to show virtual memory mappings
,
Bin Meng
,
21:35
Re: [Qemu-riscv] [Qemu-devel] [FOR 4.1 PATCH] riscv: roms: Fix make rules for building sifive_u bios
,
Palmer Dabbelt
,
19:32
Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 6/7] target/riscv: rationalise softfloat includes
,
Palmer Dabbelt
,
19:30
Re: [Qemu-riscv] [Qemu-devel] [PATCH v2] RISC-V: Ignore the S and U letters when formatting ISA strings
,
no-reply
,
19:09
Re: [Qemu-riscv] [Qemu-devel] [PATCH for 4.1] RISC-V: Ignore the S and U extensions when formatting ISA strings
,
Palmer Dabbelt
,
18:54
[Qemu-riscv] [PATCH v2] RISC-V: Ignore the S and U letters when formatting ISA strings
,
Palmer Dabbelt
,
18:54
Re: [Qemu-riscv] [PULL 04/32] target/riscv: Implement riscv_cpu_unassigned_access
,
Palmer Dabbelt
,
18:44
Re: [Qemu-riscv] [PATCH-4.2 v2 5/5] target/riscv: Fix Floating Point register names
,
Alistair Francis
,
13:10
Re: [Qemu-riscv] [Qemu-devel] [FOR 4.1 PATCH] riscv: roms: Fix make rules for building sifive_u bios
,
Alistair Francis
,
12:56
Re: [Qemu-riscv] [PATCH] riscv: hmp: Add a command to show virtual memory mappings
,
Palmer Dabbelt
,
11:18
Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 12/13] target/riscv: rationalise softfloat includes
,
Philippe Mathieu-Daudé
,
09:06
Re: [Qemu-riscv] [Qemu-devel] [FOR 4.1 PATCH] riscv: roms: Fix make rules for building sifive_u bios
,
Peter Maydell
,
09:00
[Qemu-riscv] [PATCH v3 12/13] target/riscv: rationalise softfloat includes
,
Alex Bennée
,
08:57
August 12, 2019
Re: [Qemu-riscv] [PATCH-4.2 v2 5/5] target/riscv: Fix Floating Point register names
,
Palmer Dabbelt
,
19:08
Re: [Qemu-riscv] [PATCH 1/3] riscv: sifive_u: Add support for loading initrd
,
Palmer Dabbelt
,
18:44
[Qemu-riscv] [PATCH v3] riscv: hmp: Add a command to show virtual memory mappings
,
Bin Meng
,
10:14
[Qemu-riscv] [PATCH] roms/Makefile: fix command for opensbi64-sifive_u
,
Andreas Schwab
,
08:41
Re: [Qemu-riscv] [PATCH] roms/Makefile: fix command for opensbi64-sifive_u
,
Peter Maydell
,
04:41
Re: [Qemu-riscv] [Qemu-devel] [FOR 4.1 PATCH] riscv: roms: Fix make rules for building sifive_u bios
,
Peter Maydell
,
04:38
August 11, 2019
Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 22/28] riscv: sifive_u: Generate an aliases node in the device tree
,
Alistair Francis
,
13:19
Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 25/28] riscv: hw: Remove not needed PLIC properties in device tree
,
Alistair Francis
,
13:19
Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 27/28] riscv: virt: Change create_fdt() to return void
,
Alistair Francis
,
13:18
Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 24/28] riscv: sifive_u: Support loading initramfs
,
Alistair Francis
,
13:17
Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 23/28] riscv: sifive_u: Fix broken GEM support
,
Alistair Francis
,
13:16
Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 19/28] riscv: sifive_u: Instantiate OTP memory with a serial number
,
Alistair Francis
,
13:13
Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 14/28] riscv: sifive: Implement PRCI model for FU540
,
Alistair Francis
,
13:09
Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 13/28] riscv: sifive_e: prci: Update the PRCI register block size
,
Alistair Francis
,
13:08
Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 07/28] riscv: sifive_u: Set the minimum number of cpus to 2
,
Alistair Francis
,
13:04
Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 06/28] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC
,
Alistair Francis
,
13:03
Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 04/28] riscv: hart: Extract hart realize to a separate routine
,
Alistair Francis
,
13:00
Re: [Qemu-riscv] [Qemu-devel] RISC-V: Vector && DSP Extension
,
Alistair Francis
,
12:51
Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 05/28] riscv: hart: Support heterogeneous harts population
,
Richard Henderson
,
11:57
Re: [Qemu-riscv] [PATCH v3 00/28] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine
,
Bin Meng
,
04:50
[Qemu-riscv] [PATCH v3 28/28] riscv: sifive_u: Update model and compatible strings in device tree
,
Bin Meng
,
04:07
[Qemu-riscv] [PATCH v3 27/28] riscv: virt: Change create_fdt() to return void
,
Bin Meng
,
04:07
[Qemu-riscv] [PATCH v3 25/28] riscv: hw: Remove not needed PLIC properties in device tree
,
Bin Meng
,
04:07
[Qemu-riscv] [PATCH v3 23/28] riscv: sifive_u: Fix broken GEM support
,
Bin Meng
,
04:07
[Qemu-riscv] [PATCH v3 24/28] riscv: sifive_u: Support loading initramfs
,
Bin Meng
,
04:07
[Qemu-riscv] [PATCH v3 21/28] riscv: sifive_u: Update UART and ethernet node clock properties
,
Bin Meng
,
04:07
[Qemu-riscv] [PATCH v3 22/28] riscv: sifive_u: Generate an aliases node in the device tree
,
Bin Meng
,
04:07
[Qemu-riscv] [PATCH v3 18/28] riscv: hw: Implement a model for SiFive FU540 OTP
,
Bin Meng
,
04:07
[Qemu-riscv] [PATCH v3 19/28] riscv: sifive_u: Instantiate OTP memory with a serial number
,
Bin Meng
,
04:07
[Qemu-riscv] [PATCH v3 14/28] riscv: sifive: Implement PRCI model for FU540
,
Bin Meng
,
04:07
[Qemu-riscv] [PATCH v3 17/28] riscv: sifive_u: Change UART node name in device tree
,
Bin Meng
,
04:07
[Qemu-riscv] [PATCH v3 16/28] riscv: sifive_u: Add PRCI block to the SoC
,
Bin Meng
,
04:07
[Qemu-riscv] [PATCH v3 15/28] riscv: sifive_u: Generate hfclk and rtcclk nodes
,
Bin Meng
,
04:07
[Qemu-riscv] [PATCH v3 13/28] riscv: sifive_e: prci: Update the PRCI register block size
,
Bin Meng
,
04:07
[Qemu-riscv] [PATCH v3 11/28] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}
,
Bin Meng
,
04:07
[Qemu-riscv] [PATCH v3 12/28] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming
,
Bin Meng
,
04:07
[Qemu-riscv] [PATCH v3 09/28] riscv: sifive_u: Update UART base addresses and IRQs
,
Bin Meng
,
04:07
[Qemu-riscv] [PATCH v3 10/28] riscv: sifive_u: Remove the unnecessary include of prci header
,
Bin Meng
,
04:07
[Qemu-riscv] [PATCH v3 06/28] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC
,
Bin Meng
,
04:07
[Qemu-riscv] [PATCH v3 07/28] riscv: sifive_u: Set the minimum number of cpus to 2
,
Bin Meng
,
04:07
[Qemu-riscv] [PATCH v3 08/28] riscv: sifive_u: Update PLIC hart topology configuration string
,
Bin Meng
,
04:07
[Qemu-riscv] [PATCH v3 05/28] riscv: hart: Support heterogeneous harts population
,
Bin Meng
,
04:07
[Qemu-riscv] [PATCH v3 03/28] riscv: Add a sifive_cpu.h to include both E and U cpu type defines
,
Bin Meng
,
04:07
[Qemu-riscv] [PATCH v3 04/28] riscv: hart: Extract hart realize to a separate routine
,
Bin Meng
,
04:07
[Qemu-riscv] [PATCH v3 02/28] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell
,
Bin Meng
,
04:07
[Qemu-riscv] [PATCH v3 00/28] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine
,
Bin Meng
,
04:07
[Qemu-riscv] [PATCH v3 01/28] riscv: hw: Remove superfluous "linux, phandle" property
,
Bin Meng
,
04:07
Re: [Qemu-riscv] [Qemu-devel] [FOR 4.1 PATCH] riscv: roms: Fix make rules for building sifive_u bios
,
Bin Meng
,
03:16
August 10, 2019
Re: [Qemu-riscv] [Qemu-devel] RISC-V: Vector && DSP Extension
,
LIU ZhiWei
,
09:55
Re: [Qemu-riscv] [Qemu-devel] RISC-V: Vector && DSP Extension
,
LIU ZhiWei
,
09:36
August 09, 2019
Re: [Qemu-riscv] [Qemu-devel] [PATCH 3/3] target/riscv: Remove redundant declaration pragmas
,
Alistair Francis
,
22:03
Re: [Qemu-riscv] [Qemu-devel] [PATCH 2/3] decodetree: Suppress redundant declaration warnings
,
Alistair Francis
,
22:03
Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 6/7] target/riscv: rationalise softfloat includes
,
Alistair Francis
,
21:56
Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 6/7] target/riscv: rationalise softfloat includes
,
Alistair Francis
,
21:55
Re: [Qemu-riscv] [Qemu-devel] RISC-V: Vector && DSP Extension
,
Alistair Francis
,
21:54
Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 11/28] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}
,
Alistair Francis
,
21:51
Re: [Qemu-riscv] [Qemu-devel] [PATCH v2] riscv: rv32: Root page table address can be larger than 32-bit
,
Alistair Francis
,
21:49
Re: [Qemu-riscv] [Qemu-devel] [PATCH 3/3] target/riscv: Remove redundant declaration pragmas
,
Richard Henderson
,
20:05
Re: [Qemu-riscv] [Qemu-devel] [PATCH 3/3] target/riscv: Remove redundant declaration pragmas
,
Palmer Dabbelt
,
13:43
Re: [Qemu-riscv] [PATCH 1/3] decodetree: Allow !function with no input bits
,
Richard Henderson
,
11:57
Re: [Qemu-riscv] [PATCH 1/3] decodetree: Allow !function with no input bits
,
Peter Maydell
,
11:52
Re: [Qemu-riscv] [PATCH 3/3] target/riscv: Remove redundant declaration pragmas
,
Philippe Mathieu-Daudé
,
11:48
Re: [Qemu-riscv] [PATCH 2/3] decodetree: Suppress redundant declaration warnings
,
Philippe Mathieu-Daudé
,
11:48
[Qemu-riscv] [PATCH 2/3] decodetree: Suppress redundant declaration warnings
,
Richard Henderson
,
11:42
[Qemu-riscv] [PATCH 3/3] target/riscv: Remove redundant declaration pragmas
,
Richard Henderson
,
11:42
[Qemu-riscv] [PATCH 1/3] decodetree: Allow !function with no input bits
,
Richard Henderson
,
11:42
[Qemu-riscv] [PATCH 0/3] decodetree improvements
,
Richard Henderson
,
11:42
[Qemu-riscv] [PATCH v2 6/7] target/riscv: rationalise softfloat includes
,
Alex Bennée
,
05:19
August 08, 2019
Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 17/26] exec: Replace device_endian with MemOp
,
David Gibson
,
23:07
Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 6/7] target/riscv: rationalise softfloat includes
,
Richard Henderson
,
13:57
[Qemu-riscv] [PATCH v1 6/7] target/riscv: rationalise softfloat includes
,
Alex Bennée
,
12:41
Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 12/26] hw/s390x: Hard code size with MO_{8|16|32|64}
,
Cornelia Huck
,
10:45
Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 08/26] hw/vfio: Access MemoryRegion with MemOp
,
Cornelia Huck
,
10:36
Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 07/26] hw/virtio: Access MemoryRegion with MemOp
,
Cornelia Huck
,
10:33
Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 05/26] hw/s390x: Access MemoryRegion with MemOp
,
Cornelia Huck
,
10:31
Re: [Qemu-riscv] [Qemu-devel] RISC-V: Vector && DSP Extension
,
Aleksandar Markovic
,
10:19
Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 02/26] tcg: TCGMemOp is now accelerator independent MemOp
,
Cornelia Huck
,
10:15
Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 01/26] configure: Define TARGET_ALIGNED_ONLY
,
Cornelia Huck
,
10:09
Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 11/28] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}
,
Chih-Min Chao
,
10:00
Re: [Qemu-riscv] [Qemu-devel] RISC-V: Vector && DSP Extension
,
Chih-Min Chao
,
09:50
[Qemu-riscv] RISC-V: Vector && DSP Extension
,
liuzhiwei
,
09:18
Re: [Qemu-riscv] [Qemu-devel] RISC-V: Vector && DSP Extension
,
Aleksandar Markovic
,
07:29
August 07, 2019
[Qemu-riscv] [PATCH v2] riscv: hmp: Add a command to show virtual memory mappings
,
Bin Meng
,
23:16
[Qemu-riscv] [PATCH v2] riscv: rv32: Root page table address can be larger than 32-bit
,
Bin Meng
,
22:50
Re: [Qemu-riscv] [Qemu-devel] [PATCH] riscv: rv32: Root page table address can be larger than 32-bit
,
Bin Meng
,
21:49
Re: [Qemu-riscv] [Qemu-devel] [PATCH] riscv: rv32: Root page table address can be larger than 32-bit
,
Palmer Dabbelt
,
16:55
[Qemu-riscv] [PATCH v2] RISC-V: Ignore the S and U extensions when formatting ISA strings
,
Palmer Dabbelt
,
16:35
Re: [Qemu-riscv] [Qemu-devel] RISC-V: insn32.decode: Confusing encodings
,
Richard Henderson
,
14:41
Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 20/26] memory: Access MemoryRegion with endianness
,
Richard Henderson
,
14:23
Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 20/26] memory: Access MemoryRegion with endianness
,
Paolo Bonzini
,
14:00
Re: [Qemu-riscv] [Qemu-devel] [PATCH for 4.1] RISC-V: Ignore the S and U extensions when formatting ISA strings
,
Alistair Francis
,
13:58
Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 20/26] memory: Access MemoryRegion with endianness
,
Richard Henderson
,
13:49
Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 21/26] cputlb: Replace size and endian operands for MemOp
,
Richard Henderson
,
13:38
Re: [Qemu-riscv] [Qemu-devel] [PATCH for 4.1] RISC-V: Ignore the S and U extensions when formatting ISA strings
,
Palmer Dabbelt
,
13:25
Re: [Qemu-riscv] [Qemu-devel] [PATCH for 4.1] RISC-V: Ignore the S and U extensions when formatting ISA strings
,
Peter Maydell
,
12:41
Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 18/26] exec: Delete device_endian
,
Richard Henderson
,
12:24
Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 17/26] exec: Replace device_endian with MemOp
,
Richard Henderson
,
12:23
Re: [Qemu-riscv] [Qemu-devel] [PATCH for 4.1] RISC-V: Ignore the S and U extensions when formatting ISA strings
,
Palmer Dabbelt
,
12:20
Re: [Qemu-riscv] [Qemu-devel] [PATCH for 4.1] RISC-V: Ignore the S and U extensions when formatting ISA strings
,
Peter Maydell
,
12:08
Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 16/26] exec: Map device_endian onto MemOp
,
Richard Henderson
,
12:07
Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 16/26] exec: Map device_endian onto MemOp
,
Richard Henderson
,
12:00
Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 16/26] exec: Map device_endian onto MemOp
,
Richard Henderson
,
11:55
Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 14/26] exec: Hard code size with MO_{8|16|32|64}
,
Richard Henderson
,
11:48
Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 13/26] target/mips: Hard code size with MO_{8|16|32|64}
,
Richard Henderson
,
11:48
Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 12/26] hw/s390x: Hard code size with MO_{8|16|32|64}
,
Richard Henderson
,
11:47
Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 11/26] memory: Access MemoryRegion with MemOp
,
Richard Henderson
,
11:38
Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 10/26] cputlb: Access MemoryRegion with MemOp
,
Richard Henderson
,
11:33
Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 03/26] memory: Introduce size_memop
,
Richard Henderson
,
11:31
Re: [Qemu-riscv] [PATCH for 4.1] RISC-V: Ignore the S and U extensions when formatting ISA strings
,
Paul Walmsley
,
11:27
Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 19/26] exec: Delete DEVICE_HOST_ENDIAN
,
Richard Henderson
,
11:21
[Qemu-riscv] [PATCH for 4.1] RISC-V: Ignore the S and U extensions when formatting ISA strings
,
Palmer Dabbelt
,
11:00
Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 06/26] hw/intc/armv7m_nic: Access MemoryRegion with MemOp
,
tony.nguyen
,
09:06
Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 19/26] exec: Delete DEVICE_HOST_ENDIAN
,
Paolo Bonzini
,
09:06
[Qemu-riscv] [Qemu-devel] [PATCH v6 16/26] exec: Map device_endian onto MemOp
,
tony.nguyen
,
09:06
[Qemu-riscv] [Qemu-devel] [PATCH v6 11/26] memory: Access MemoryRegion with MemOp
,
tony.nguyen
,
09:06
[Qemu-riscv] [Qemu-devel] [PATCH v6 09/26] exec: Access MemoryRegion with MemOp
,
tony.nguyen
,
09:06
[Qemu-riscv] [Qemu-devel] [PATCH v6 04/26] target/mips: Access MemoryRegion with MemOp
,
tony.nguyen
,
09:06
[Qemu-riscv] [Qemu-devel] [PATCH v6 18/26] exec: Delete device_endian
,
tony.nguyen
,
09:06
Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 09/26] exec: Access MemoryRegion with MemOp
,
tony.nguyen
,
09:06
Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 04/26] target/mips: Access MemoryRegion with MemOp
,
tony.nguyen
,
09:06
[Qemu-riscv] [Qemu-devel] [PATCH v6 19/26] exec: Delete DEVICE_HOST_ENDIAN
,
tony.nguyen
,
09:06
[Qemu-riscv] [Qemu-devel] [PATCH v6 01/26] configure: Define TARGET_ALIGNED_ONLY
,
tony.nguyen
,
09:06
[Qemu-riscv] [Qemu-devel] [PATCH v6 00/26] Invert Endian bit in SPARCv9 MMU TTE
,
tony.nguyen
,
09:06
Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 26/26] target/sparc: sun4u Invert Endian TTE bit
,
tony.nguyen
,
09:05
Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 10/26] cputlb: Access MemoryRegion with MemOp
,
tony.nguyen
,
09:05
Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 00/26] Invert Endian bit in SPARCv9 MMU TTE
,
tony.nguyen
,
09:05
Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 15/26] build: Correct non-common common-obj-* to obj-*
,
Paolo Bonzini
,
09:05
[Qemu-riscv] [Qemu-devel] [PATCH v6 26/26] target/sparc: sun4u Invert Endian TTE bit
,
tony.nguyen
,
09:05
[Qemu-riscv] [Qemu-devel] [PATCH v6 20/26] memory: Access MemoryRegion with endianness
,
tony.nguyen
,
09:05
[Qemu-riscv] [Qemu-devel] [PATCH v6 23/26] cpu: TLB_FLAGS_MASK bit to force memory slow path
,
tony.nguyen
,
09:05
[Qemu-riscv] [Qemu-devel] [PATCH v6 22/26] memory: Single byte swap along the I/O path
,
tony.nguyen
,
09:05
[Qemu-riscv] [Qemu-devel] [PATCH v6 17/26] exec: Replace device_endian with MemOp
,
tony.nguyen
,
09:05
[Qemu-riscv] [Qemu-devel] [PATCH v6 05/26] hw/s390x: Access MemoryRegion with MemOp
,
tony.nguyen
,
09:05
[Qemu-riscv] [Qemu-devel] [PATCH v6 03/26] memory: Introduce size_memop
,
tony.nguyen
,
09:05
Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 00/26] Invert Endian bit in SPARCv9 MMU TTE
,
Philippe Mathieu-Daudé
,
09:05
[Qemu-riscv] [Qemu-devel] [PATCH v6 12/26] hw/s390x: Hard code size with MO_{8|16|32|64}
,
tony.nguyen
,
09:05
[Qemu-riscv] [Qemu-devel] [PATCH v6 25/26] target/sparc: Add TLB entry with attributes
,
tony.nguyen
,
09:05
[Qemu-riscv] [Qemu-devel] [PATCH v6 14/26] exec: Hard code size with MO_{8|16|32|64}
,
tony.nguyen
,
09:05
[Qemu-riscv] [Qemu-devel] [PATCH v6 13/26] target/mips: Hard code size with MO_{8|16|32|64}
,
tony.nguyen
,
09:05
Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 20/26] memory: Access MemoryRegion with endianness
,
Paolo Bonzini
,
09:05
[Qemu-riscv] [Qemu-devel] [PATCH v6 24/26] cputlb: Byte swap memory transaction attribute
,
tony.nguyen
,
09:05
[Qemu-riscv] [Qemu-devel] [PATCH v6 21/26] cputlb: Replace size and endian operands for MemOp
,
tony.nguyen
,
09:05
[Qemu-riscv] [Qemu-devel] [PATCH v6 15/26] build: Correct non-common common-obj-* to obj-*
,
tony.nguyen
,
09:05
[Qemu-riscv] [Qemu-devel] [PATCH v6 10/26] cputlb: Access MemoryRegion with MemOp
,
tony.nguyen
,
09:05
[Qemu-riscv] [Qemu-devel] [PATCH v6 08/26] hw/vfio: Access MemoryRegion with MemOp
,
tony.nguyen
,
09:05
[Qemu-riscv] [Qemu-devel] [PATCH v6 07/26] hw/virtio: Access MemoryRegion with MemOp
,
tony.nguyen
,
09:05
Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 00/26] Invert Endian bit in SPARCv9 MMU TTE
,
Philippe Mathieu-Daudé
,
09:05
[Qemu-riscv] [Qemu-devel] [PATCH v6 06/26] hw/intc/armv7m_nic: Access MemoryRegion with MemOp
,
tony.nguyen
,
09:05
[Qemu-riscv] [Qemu-devel] [PATCH v6 02/26] tcg: TCGMemOp is now accelerator independent MemOp
,
tony.nguyen
,
09:05
Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 11/28] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}
,
Bin Meng
,
06:11
Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 07/28] riscv: sifive_u: Set the minimum number of cpus to 2
,
Bin Meng
,
06:05
Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 03/28] riscv: Add a sifive_cpu.h to include both E and U cpu type defines
,
Philippe Mathieu-Daudé
,
05:50
Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 12/28] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming
,
Philippe Mathieu-Daudé
,
05:49
Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 27/28] riscv: virt: Change create_fdt() to return void
,
Philippe Mathieu-Daudé
,
05:48
Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 07/28] riscv: sifive_u: Set the minimum number of cpus to 2
,
Philippe Mathieu-Daudé
,
05:46
Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 09/28] riscv: sifive_u: Update UART base addresses
,
Bin Meng
,
05:38
Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 09/28] riscv: sifive_u: Update UART base addresses
,
Chih-Min Chao
,
05:25
Re: [Qemu-riscv] [PATCH v2 27/28] riscv: virt: Change create_fdt() to return void
,
Chih-Min Chao
,
05:05
Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 24/28] riscv: sifive_u: Support loading initramfs
,
Chih-Min Chao
,
05:04
Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 13/28] riscv: sifive_e: prci: Update the PRCI register block size
,
Chih-Min Chao
,
05:00
Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 12/28] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming
,
Chih-Min Chao
,
04:59
Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 11/28] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}
,
Chih-Min Chao
,
04:54
[Qemu-riscv] [PATCH v2 21/28] riscv: sifive_u: Update UART and ethernet node clock properties
,
Bin Meng
,
03:46
[Qemu-riscv] [PATCH v2 28/28] riscv: sifive_u: Update model and compatible strings in device tree
,
Bin Meng
,
03:46
[Qemu-riscv] [PATCH v2 27/28] riscv: virt: Change create_fdt() to return void
,
Bin Meng
,
03:46
[Qemu-riscv] [PATCH v2 23/28] riscv: sifive_u: Fix broken GEM support
,
Bin Meng
,
03:46
[Qemu-riscv] [PATCH v2 24/28] riscv: sifive_u: Support loading initramfs
,
Bin Meng
,
03:46
[Qemu-riscv] [PATCH v2 18/28] riscv: hw: Implement a model for SiFive FU540 OTP
,
Bin Meng
,
03:46
[Qemu-riscv] [PATCH v2 25/28] riscv: hw: Remove not needed PLIC properties in device tree
,
Bin Meng
,
03:46
[Qemu-riscv] [PATCH v2 14/28] riscv: sifive: Implement PRCI model for FU540
,
Bin Meng
,
03:46
[Qemu-riscv] [PATCH v2 16/28] riscv: sifive_u: Add PRCI block to the SoC
,
Bin Meng
,
03:46
[Qemu-riscv] [PATCH v2 17/28] riscv: sifive_u: Change UART node name in device tree
,
Bin Meng
,
03:46
[Qemu-riscv] [PATCH v2 22/28] riscv: sifive_u: Generate an aliases node in the device tree
,
Bin Meng
,
03:46
[Qemu-riscv] [PATCH v2 13/28] riscv: sifive_e: prci: Update the PRCI register block size
,
Bin Meng
,
03:46
[Qemu-riscv] [PATCH v2 05/28] riscv: hart: Support heterogeneous harts population
,
Bin Meng
,
03:46
[Qemu-riscv] [PATCH v2 19/28] riscv: sifive_u: Instantiate OTP memory with a serial number
,
Bin Meng
,
03:46
[Qemu-riscv] [PATCH v2 06/28] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC
,
Bin Meng
,
03:46
[Qemu-riscv] [PATCH v2 10/28] riscv: sifive_u: Remove the unnecessary include of prci header
,
Bin Meng
,
03:46
[Qemu-riscv] [PATCH v2 11/28] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}
,
Bin Meng
,
03:45
[Qemu-riscv] [PATCH v2 15/28] riscv: sifive_u: Generate hfclk and rtcclk nodes
,
Bin Meng
,
03:45
[Qemu-riscv] [PATCH v2 08/28] riscv: sifive_u: Update PLIC hart topology configuration string
,
Bin Meng
,
03:45
[Qemu-riscv] [PATCH v2 12/28] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming
,
Bin Meng
,
03:45
[Qemu-riscv] [PATCH v2 03/28] riscv: Add a sifive_cpu.h to include both E and U cpu type defines
,
Bin Meng
,
03:45
[Qemu-riscv] [PATCH v2 09/28] riscv: sifive_u: Update UART base addresses
,
Bin Meng
,
03:45
[Qemu-riscv] [PATCH v2 07/28] riscv: sifive_u: Set the minimum number of cpus to 2
,
Bin Meng
,
03:45
[Qemu-riscv] [PATCH v2 04/28] riscv: hart: Extract hart realize to a separate routine
,
Bin Meng
,
03:45
[Qemu-riscv] [PATCH v2 02/28] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell
,
Bin Meng
,
03:45
[Qemu-riscv] [PATCH v2 00/28] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine
,
Bin Meng
,
03:45
[Qemu-riscv] [PATCH v2 01/28] riscv: hw: Remove superfluous "linux, phandle" property
,
Bin Meng
,
03:45
August 06, 2019
Re: [Qemu-riscv] [Qemu-devel] [PATCH] riscv: sifive_e: Correct various SoC IP block sizes
,
Bin Meng
,
22:53
Re: [Qemu-riscv] [Qemu-devel] [PATCH] riscv: sifive_e: Correct various SoC IP block sizes
,
Bin Meng
,
21:36
Re: [Qemu-riscv] [Qemu-devel] [PATCH] riscv: sifive_e: Correct various SoC IP block sizes
,
Philippe Mathieu-Daudé
,
17:07
[Qemu-riscv] RISC-V: insn32.decode: Confusing encodings
,
Maxim Blinov
,
08:49
August 05, 2019
Re: [Qemu-riscv] [Qemu-devel] [PATCH 23/28] riscv: sifive: Move sifive_mmio_emulate() to a common place
,
Alistair Francis
,
20:29
Re: [Qemu-riscv] [Qemu-devel] [PATCH 28/28] riscv: sifive_u: Update model and compatible strings in device tree
,
Alistair Francis
,
20:26
Re: [Qemu-riscv] [Qemu-devel] [PATCH 17/28] riscv: sifive_u: Change UART node name in device tree
,
Alistair Francis
,
20:24
Re: [Qemu-riscv] [Qemu-devel] [PATCH 09/28] riscv: sifive_u: Update UART base addresses
,
Alistair Francis
,
20:23
Re: [Qemu-riscv] [Qemu-devel] [PATCH 12/28] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming
,
Alistair Francis
,
20:22
Re: [Qemu-riscv] [Qemu-devel] [PATCH 10/28] riscv: sifive_u: Remove the unnecessary include of prci header
,
Alistair Francis
,
20:21
Re: [Qemu-riscv] [Qemu-devel] [PATCH 08/28] riscv: sifive_u: Update PLIC hart topology configuration string
,
Alistair Francis
,
20:20
Re: [Qemu-riscv] [Qemu-devel] [PATCH 07/28] riscv: sifive_u: Set the minimum number of cpus to 2
,
Alistair Francis
,
20:20
Re: [Qemu-riscv] [Qemu-devel] [PATCH 03/28] riscv: Add a sifive_cpu.h to include both E and U cpu type defines
,
Alistair Francis
,
20:18
Re: [Qemu-riscv] [Qemu-devel] [PATCH 02/28] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell
,
Alistair Francis
,
20:17
Re: [Qemu-riscv] [Qemu-devel] [PATCH 01/28] riscv: hw: Remove superfluous "linux, phandle" property
,
Alistair Francis
,
20:15
Re: [Qemu-riscv] [Qemu-devel] [PATCH] riscv: sifive_e: Correct various SoC IP block sizes
,
Alistair Francis
,
13:55
Re: [Qemu-riscv] [Qemu-devel] [PATCH-4.2 v1 6/6] target/riscv: Fix Floating Point register names
,
Alistair Francis
,
13:53
Re: [Qemu-riscv] [Qemu-devel] [FOR 4.1 PATCH] riscv: roms: Fix make rules for building sifive_u bios
,
Alistair Francis
,
13:05
Re: [Qemu-riscv] [PATCH 26/28] riscv: hw: Update PLIC device tree
,
Jonathan Behrens
,
13:01
Re: [Qemu-riscv] [PATCH 09/28] riscv: sifive_u: Update UART base addresses
,
Jonathan Behrens
,
12:44
Re: [Qemu-riscv] [PATCH 07/28] riscv: sifive_u: Set the minimum number of cpus to 2
,
Jonathan Behrens
,
12:42
Re: [Qemu-riscv] [PATCH 2/2] riscv: sifive_u: Update the plic hart config to support multicore
,
Fabien Chouteau
,
12:19
Re: [Qemu-riscv] [PATCH 2/2] riscv: sifive_u: Update the plic hart config to support multicore
,
Bin Meng
,
12:10
Re: [Qemu-riscv] [Qemu-devel] [PATCH 2/2] riscv: sifive_u: Update the plic hart config to support multicore
,
Bin Meng
,
12:09
[Qemu-riscv] [PATCH 28/28] riscv: sifive_u: Update model and compatible strings in device tree
,
Bin Meng
,
12:01
[Qemu-riscv] [PATCH 24/28] riscv: sifive_u: Fix broken GEM support
,
Bin Meng
,
12:01
[Qemu-riscv] [PATCH 23/28] riscv: sifive: Move sifive_mmio_emulate() to a common place
,
Bin Meng
,
12:01
[Qemu-riscv] [PATCH 25/28] riscv: sifive_u: Support loading initramfs
,
Bin Meng
,
12:01
[Qemu-riscv] [PATCH 17/28] riscv: sifive_u: Change UART node name in device tree
,
Bin Meng
,
12:01
[Qemu-riscv] [PATCH 16/28] riscv: sifive_u: Add PRCI block to the SoC
,
Bin Meng
,
12:01
[Qemu-riscv] [PATCH 15/28] riscv: sifive_u: Generate hfclk and rtcclk nodes
,
Bin Meng
,
12:01
[Qemu-riscv] [PATCH 22/28] riscv: sifive_u: Generate an aliases node in the device tree
,
Bin Meng
,
12:01
[Qemu-riscv] [PATCH 21/28] riscv: sifive_u: Update UART and ethernet node clock properties
,
Bin Meng
,
12:01
[Qemu-riscv] [PATCH 27/28] riscv: virt: Change create_fdt() to return void
,
Bin Meng
,
12:01
[Qemu-riscv] [PATCH 18/28] riscv: hw: Implement a model for SiFive FU540 OTP
,
Bin Meng
,
12:01
[Qemu-riscv] [PATCH 14/28] riscv: sifive: Implement PRCI model for FU540
,
Bin Meng
,
12:01
[Qemu-riscv] [PATCH 26/28] riscv: hw: Update PLIC device tree
,
Bin Meng
,
12:01
[Qemu-riscv] [PATCH 12/28] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming
,
Bin Meng
,
12:01
[Qemu-riscv] [PATCH 10/28] riscv: sifive_u: Remove the unnecessary include of prci header
,
Bin Meng
,
12:01
[Qemu-riscv] [PATCH 11/28] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}
,
Bin Meng
,
12:01
[Qemu-riscv] [PATCH 08/28] riscv: sifive_u: Update PLIC hart topology configuration string
,
Bin Meng
,
12:00
[Qemu-riscv] [PATCH 06/28] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC
,
Bin Meng
,
12:00
[Qemu-riscv] [PATCH 13/28] riscv: sifive_e: prci: Update the PRCI register block size
,
Bin Meng
,
12:00
[Qemu-riscv] [PATCH 09/28] riscv: sifive_u: Update UART base addresses
,
Bin Meng
,
12:00
[Qemu-riscv] [PATCH 02/28] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell
,
Bin Meng
,
12:00
[Qemu-riscv] [PATCH 04/28] riscv: hart: Extract hart realize to a separate routine
,
Bin Meng
,
12:00
[Qemu-riscv] [PATCH 07/28] riscv: sifive_u: Set the minimum number of cpus to 2
,
Bin Meng
,
12:00
[Qemu-riscv] [PATCH 05/28] riscv: hart: Support heterogeneous harts population
,
Bin Meng
,
12:00
[Qemu-riscv] [PATCH 03/28] riscv: Add a sifive_cpu.h to include both E and U cpu type defines
,
Bin Meng
,
12:00
[Qemu-riscv] [PATCH 00/28] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine
,
Bin Meng
,
12:00
[Qemu-riscv] [PATCH 01/28] riscv: hw: Remove superfluous "linux, phandle" property
,
Bin Meng
,
12:00
Re: [Qemu-riscv] [FOR 4.1 PATCH] riscv: roms: Fix make rules for building sifive_u bios
,
Chih-Min Chao
,
03:13
Re: [Qemu-riscv] [Qemu-devel] [PATCH-4.2 v2 3/5] target/riscv: Create function to test if FP is enabled
,
Chih-Min Chao
,
02:59
Re: [Qemu-riscv] [PATCH] riscv: sifive_e: Correct various SoC IP block sizes
,
Bin Meng
,
02:44
Re: [Qemu-riscv] [Qemu-devel] [PATCH-4.2 v2 4/5] target/riscv: Update the Hypervisor CSRs to v0.4
,
Chih-Min Chao
,
02:19
Re: [Qemu-riscv] [PATCH] riscv: sifive_e: Correct various SoC IP block sizes
,
Chih-Min Chao
,
02:14
August 04, 2019
Re: [Qemu-riscv] [FOR 4.1 PATCH] riscv: roms: Fix make rules for building sifive_u bios
,
Bin Meng
,
11:11
August 03, 2019
[Qemu-riscv] [FOR 4.1 PATCH] riscv: roms: Fix make rules for building sifive_u bios
,
Bin Meng
,
02:08
August 02, 2019
[Qemu-riscv] [PATCH] riscv: sifive_e: Correct various SoC IP block sizes
,
Bin Meng
,
20:27
Re: [Qemu-riscv] [PATCH] riscv: hmp: Add a command to show virtual memory mappings
,
Dr. David Alan Gilbert
,
17:01
August 01, 2019
Re: [Qemu-riscv] [PULL 04/32] target/riscv: Implement riscv_cpu_unassigned_access
,
Peter Maydell
,
11:40
Re: [Qemu-riscv] [Qemu-devel] [PATCH] riscv: rv32: Root page table address can be larger than 32-bit
,
Bin Meng
,
10:58
Re: [Qemu-riscv] [Qemu-devel] [PATCH] riscv: rv32: Root page table address can be larger than 32-bit
,
Richard Henderson
,
10:16
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