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[PATCH v2 06/35] target/riscv: Add the virtulisation mode
From: |
Alistair Francis |
Subject: |
[PATCH v2 06/35] target/riscv: Add the virtulisation mode |
Date: |
Fri, 31 Jan 2020 17:01:51 -0800 |
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
---
target/riscv/cpu.h | 4 ++++
target/riscv/cpu_bits.h | 3 +++
target/riscv/cpu_helper.c | 18 ++++++++++++++++++
3 files changed, 25 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index c7f7ae5c38..a9cbd8584e 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -117,6 +117,8 @@ struct CPURISCVState {
#ifndef CONFIG_USER_ONLY
target_ulong priv;
+ /* This contains QEMU specific information about the virt state. */
+ target_ulong virt;
target_ulong resetvec;
target_ulong mhartid;
@@ -269,6 +271,8 @@ int riscv_cpu_gdb_read_register(CPUState *cpu, uint8_t
*buf, int reg);
int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
bool riscv_cpu_fp_enabled(CPURISCVState *env);
+bool riscv_cpu_virt_enabled(CPURISCVState *env);
+void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index eeaa03c0f8..2cdb0de4fe 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -430,6 +430,9 @@
#define PRV_H 2 /* Reserved */
#define PRV_M 3
+/* Virtulisation Register Fields */
+#define VIRT_ONOFF 1
+
/* RV32 satp CSR field masks */
#define SATP32_MODE 0x80000000
#define SATP32_ASID 0x7fc00000
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 8f746fb06f..5844e543f3 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -82,6 +82,24 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env)
return false;
}
+bool riscv_cpu_virt_enabled(CPURISCVState *env)
+{
+ if (!riscv_has_ext(env, RVH)) {
+ return false;
+ }
+
+ return get_field(env->virt, VIRT_ONOFF);
+}
+
+void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable)
+{
+ if (!riscv_has_ext(env, RVH)) {
+ return;
+ }
+
+ env->virt = set_field(env->virt, VIRT_ONOFF, enable);
+}
+
int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts)
{
CPURISCVState *env = &cpu->env;
--
2.25.0
- [PATCH v2 00/35] Add RISC-V Hypervisor Extension v0.5, Alistair Francis, 2020/01/31
- [PATCH v2 01/35] target/riscv: Convert MIP CSR to target_ulong, Alistair Francis, 2020/01/31
- [PATCH v2 02/35] target/riscv: Add the Hypervisor extension, Alistair Francis, 2020/01/31
- [PATCH v2 03/35] target/riscv: Add the Hypervisor CSRs to CPUState, Alistair Francis, 2020/01/31
- [PATCH v2 04/35] target/riscv: Add support for the new execption numbers, Alistair Francis, 2020/01/31
- [PATCH v2 05/35] target/riscv: Rename the H irqs to VS irqs, Alistair Francis, 2020/01/31
- [PATCH v2 06/35] target/riscv: Add the virtulisation mode,
Alistair Francis <=
- [PATCH v2 07/35] target/riscv: Add the force HS exception mode, Alistair Francis, 2020/01/31
- [PATCH v2 08/35] target/riscv: Fix CSR perm checking for HS mode, Alistair Francis, 2020/01/31
- [PATCH v2 09/35] target/riscv: Print priv and virt in disas log, Alistair Francis, 2020/01/31
- [PATCH v2 10/35] target/riscv: Dump Hypervisor registers if enabled, Alistair Francis, 2020/01/31
- [PATCH v2 11/35] target/riscv: Add Hypervisor CSR access functions, Alistair Francis, 2020/01/31
- [PATCH v2 12/35] target/riscv: Add Hypervisor virtual CSRs accesses, Alistair Francis, 2020/01/31
- [PATCH v2 13/35] target/riscv: Add Hypervisor machine CSRs accesses, Alistair Francis, 2020/01/31
- [PATCH v2 14/35] target/riscv: Add virtual register swapping function, Alistair Francis, 2020/01/31
- [PATCH v2 17/35] target/riscv: Extend the SIP CSR to support virtulisation, Alistair Francis, 2020/01/31
- [PATCH v2 15/35] target/riscv: Set VS bits in mideleg for Hyp extension, Alistair Francis, 2020/01/31